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Emit target specific nodes to handle palignr. Do not touch it for MMX versions yet.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113056 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2010-09-04 02:36:07 +00:00
parent c800c0d25f
commit aace0f295b
1 changed files with 10 additions and 2 deletions
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12
lib/Target/X86/X86ISelLowering.cpp
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@ -2592,6 +2592,7 @@ static bool isTargetShuffle(unsigned Opcode) {
case X86ISD::PSHUFHW:
case X86ISD::PSHUFLW:
case X86ISD::SHUFPD:
case X86ISD::PALIGN:
case X86ISD::SHUFPS:
case X86ISD::MOVLHPS:
case X86ISD::MOVLHPD:
@ -2648,6 +2649,7 @@ static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
switch(Opc) {
default: llvm_unreachable("Unknown x86 shuffle node");
case X86ISD::PALIGN:
case X86ISD::SHUFPD:
case X86ISD::SHUFPS:
return DAG.getNode(Opc, dl, VT, V1, V2,
@ -5262,6 +5264,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
bool V2IsSplat = false;
bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
MachineFunction &MF = DAG.getMachineFunction();
bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
@ -5469,10 +5472,14 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
return isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ? Op : SDValue();
// FIXME: pshufb, blends, shifts.
if (VT.getVectorNumElements() == 2 ||
isPALIGNRMask(M, VT, Subtarget->hasSSSE3()))
if (VT.getVectorNumElements() == 2)
return Op;
if (isPALIGNRMask(M, VT, HasSSSE3))
return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
X86::getShufflePALIGNRImmediate(SVOp),
DAG);
if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
SVOp->getSplatIndex() == 0 && V2IsUndef) {
if (VT == MVT::v2f64)
@ -10780,6 +10787,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
case X86ISD::SHUFPS: // Handle all target specific shuffles
case X86ISD::SHUFPD:
case X86ISD::PALIGN:
case X86ISD::PUNPCKHBW:
case X86ISD::PUNPCKHWD:
case X86ISD::PUNPCKHDQ: