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SI, DI, BP, and SP don't have 8-bit sub-registers in x86 mode.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133308 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-06-17 23:15:00 +00:00
parent 5e687ac615
commit aad458d57f
1 changed files with 9 additions and 2 deletions
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11
lib/Target/X86/X86RegisterInfo.cpp
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@ -517,13 +517,20 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
// Reserve the registers that only exist in 64-bit mode.
if (!Is64Bit) {
// These 8-bit registers are part of the x86-64 extension even though their
// super-registers are old 32-bits.
Reserved.set(X86::SIL);
Reserved.set(X86::DIL);
Reserved.set(X86::BPL);
Reserved.set(X86::SPL);
for (unsigned n = 0; n != 8; ++n) {
// R8, R9, ...
const unsigned GPR64[] = {
X86::R8, X86::R9, X86::R10, X86::R11,
X86::R12, X86::R13, X86::R14, X86::R15
};
for (const unsigned *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI;
++AI)
for (const unsigned *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI; ++AI)
Reserved.set(Reg);
// XMM8, XMM9, ...