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SI, DI, BP, and SP don't have 8-bit sub-registers in x86 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133308 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -517,13 +517,20 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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// Reserve the registers that only exist in 64-bit mode.
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if (!Is64Bit) {
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// These 8-bit registers are part of the x86-64 extension even though their
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// super-registers are old 32-bits.
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Reserved.set(X86::SIL);
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Reserved.set(X86::DIL);
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Reserved.set(X86::BPL);
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Reserved.set(X86::SPL);
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for (unsigned n = 0; n != 8; ++n) {
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// R8, R9, ...
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const unsigned GPR64[] = {
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X86::R8, X86::R9, X86::R10, X86::R11,
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X86::R12, X86::R13, X86::R14, X86::R15
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};
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for (const unsigned *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI;
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++AI)
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for (const unsigned *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI; ++AI)
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Reserved.set(Reg);
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// XMM8, XMM9, ...
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