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[mips] [IAS] Add partial support for the ULW pseudo-instruction.
Summary: This only adds support for ULW of an immediate address with/without a source register. It does not include support for ULW of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9663 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240782 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Toma Tabacu
parent
37c948ae79
commit
aafe2ca7d5
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@ -218,6 +218,9 @@ class MipsAsmParser : public MCTargetAsmParser {
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bool expandUlhu(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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bool expandUlw(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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void createNop(bool hasShortDelaySlot, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions);
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@ -1649,6 +1652,7 @@ bool MipsAsmParser::needsExpansion(MCInst &Inst) {
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case Mips::BGEU:
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case Mips::BGTU:
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case Mips::Ulhu:
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case Mips::Ulw:
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return true;
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default:
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return false;
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@ -1689,6 +1693,8 @@ bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
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return expandCondBranches(Inst, IDLoc, Instructions);
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case Mips::Ulhu:
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return expandUlhu(Inst, IDLoc, Instructions);
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case Mips::Ulw:
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return expandUlw(Inst, IDLoc, Instructions);
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}
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}
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@ -2582,6 +2588,79 @@ bool MipsAsmParser::expandUlhu(MCInst &Inst, SMLoc IDLoc,
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return false;
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}
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bool MipsAsmParser::expandUlw(MCInst &Inst, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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if (hasMips32r6() || hasMips64r6()) {
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Error(IDLoc, "instruction not supported on mips32r6 or mips64r6");
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return false;
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}
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const MCOperand &DstRegOp = Inst.getOperand(0);
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assert(DstRegOp.isReg() && "expected register operand kind");
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const MCOperand &SrcRegOp = Inst.getOperand(1);
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assert(SrcRegOp.isReg() && "expected register operand kind");
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const MCOperand &OffsetImmOp = Inst.getOperand(2);
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assert(OffsetImmOp.isImm() && "expected immediate operand kind");
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unsigned SrcReg = SrcRegOp.getReg();
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int64_t OffsetValue = OffsetImmOp.getImm();
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unsigned ATReg = 0;
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// When the value of offset+3 does not fit in 16 bits, we have to load the
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// offset in AT, (D)ADDu the original source register (if there was one), and
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// then use AT as the source register for the generated LWL and LWR.
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bool LoadedOffsetInAT = false;
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if (!isInt<16>(OffsetValue + 3) || !isInt<16>(OffsetValue)) {
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ATReg = getATReg(IDLoc);
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if (!ATReg)
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return true;
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LoadedOffsetInAT = true;
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warnIfNoMacro(IDLoc);
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if (loadImmediate(OffsetValue, ATReg, Mips::NoRegister, !ABI.ArePtrs64bit(),
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IDLoc, Instructions))
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return true;
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// NOTE: We do this (D)ADDu here instead of doing it in loadImmediate()
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// because it will make our output more similar to GAS'. For example,
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// generating an "ori $1, $zero, 32768" followed by an "addu $1, $1, $9",
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// instead of just an "ori $1, $9, 32768".
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// NOTE: If there is no source register specified in the ULW, the parser
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// will interpret it as $0.
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if (SrcReg != Mips::ZERO && SrcReg != Mips::ZERO_64)
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createAddu(ATReg, ATReg, SrcReg, ABI.ArePtrs64bit(), Instructions);
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}
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unsigned FinalSrcReg = LoadedOffsetInAT ? ATReg : SrcReg;
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int64_t LeftLoadOffset = 0, RightLoadOffset = 0;
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if (isLittle()) {
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LeftLoadOffset = LoadedOffsetInAT ? 3 : (OffsetValue + 3);
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RightLoadOffset = LoadedOffsetInAT ? 0 : OffsetValue;
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} else {
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LeftLoadOffset = LoadedOffsetInAT ? 0 : OffsetValue;
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RightLoadOffset = LoadedOffsetInAT ? 3 : (OffsetValue + 3);
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}
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MCInst LeftLoadInst;
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LeftLoadInst.setOpcode(Mips::LWL);
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LeftLoadInst.addOperand(DstRegOp);
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LeftLoadInst.addOperand(MCOperand::createReg(FinalSrcReg));
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LeftLoadInst.addOperand(MCOperand::createImm(LeftLoadOffset));
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Instructions.push_back(LeftLoadInst);
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MCInst RightLoadInst;
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RightLoadInst.setOpcode(Mips::LWR);
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RightLoadInst.addOperand(DstRegOp);
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RightLoadInst.addOperand(MCOperand::createReg(FinalSrcReg));
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RightLoadInst.addOperand(MCOperand::createImm(RightLoadOffset ));
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Instructions.push_back(RightLoadInst);
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return false;
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}
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void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc,
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SmallVectorImpl<MCInst> &Instructions) {
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MCInst NopInst;
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@ -1716,6 +1716,9 @@ def BGTU : CondBranchPseudo<"bgtu">;
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def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
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"ulhu\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6;
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def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
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"ulw\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6;
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//===----------------------------------------------------------------------===//
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// Arbitrary patterns that map to one or more instructions
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//===----------------------------------------------------------------------===//
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@ -36,3 +36,16 @@
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ulhu $5, 2
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# 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
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# 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
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.set mips32r6
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ulw $5, 0
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# 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
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# 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
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.set mips32
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ulw $5, 1
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# 32-BIT-NOT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
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# 64-BIT-NOT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
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.set mips64r6
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ulw $5, 2
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# 32-BIT: :[[@LINE-1]]:3: error: instruction not supported on mips32r6 or mips64r6
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# 64-BIT: :[[@LINE-2]]:3: error: instruction not supported on mips32r6 or mips64r6
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@ -382,5 +382,141 @@
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# CHECK-LE: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
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# CHECK-LE: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
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# Test ULW with immediate operand.
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ulw $8, 0
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# CHECK-BE: lwl $8, 0($zero) # encoding: [0x88,0x08,0x00,0x00]
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# CHECK-BE: lwr $8, 3($zero) # encoding: [0x98,0x08,0x00,0x03]
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# CHECK-LE: lwl $8, 3($zero) # encoding: [0x03,0x00,0x08,0x88]
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# CHECK-LE: lwr $8, 0($zero) # encoding: [0x00,0x00,0x08,0x98]
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ulw $8, 2
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# CHECK-BE: lwl $8, 2($zero) # encoding: [0x88,0x08,0x00,0x02]
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# CHECK-BE: lwr $8, 5($zero) # encoding: [0x98,0x08,0x00,0x05]
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# CHECK-LE: lwl $8, 5($zero) # encoding: [0x05,0x00,0x08,0x88]
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# CHECK-LE: lwr $8, 2($zero) # encoding: [0x02,0x00,0x08,0x98]
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ulw $8, 0x8000
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# CHECK-BE: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00]
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# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00]
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# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03]
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# CHECK-LE: ori $1, $zero, 32768 # encoding: [0x00,0x80,0x01,0x34]
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# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
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# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
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ulw $8, -0x8000
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# CHECK-BE: lwl $8, -32768($zero) # encoding: [0x88,0x08,0x80,0x00]
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# CHECK-BE: lwr $8, -32765($zero) # encoding: [0x98,0x08,0x80,0x03]
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# CHECK-LE: lwl $8, -32765($zero) # encoding: [0x03,0x80,0x08,0x88]
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# CHECK-LE: lwr $8, -32768($zero) # encoding: [0x00,0x80,0x08,0x98]
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ulw $8, 0x10000
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# CHECK-BE: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01]
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# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00]
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# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03]
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# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
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# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
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# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
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ulw $8, 0x18888
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# CHECK-BE: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01]
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# CHECK-BE: ori $1, $1, 34952 # encoding: [0x34,0x21,0x88,0x88]
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# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00]
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# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03]
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# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
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# CHECK-LE: ori $1, $1, 34952 # encoding: [0x88,0x88,0x21,0x34]
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# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
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# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
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ulw $8, -32771
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# CHECK-BE: lui $1, 65535 # encoding: [0x3c,0x01,0xff,0xff]
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# CHECK-BE: ori $1, $1, 32765 # encoding: [0x34,0x21,0x7f,0xfd]
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# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00]
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# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03]
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# CHECK-LE: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c]
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# CHECK-LE: ori $1, $1, 32765 # encoding: [0xfd,0x7f,0x21,0x34]
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# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
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# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
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ulw $8, 32765
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# CHECK-BE: ori $1, $zero, 32765 # encoding: [0x34,0x01,0x7f,0xfd]
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# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00]
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# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03]
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# CHECK-LE: ori $1, $zero, 32765 # encoding: [0xfd,0x7f,0x01,0x34]
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# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
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# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
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# Test ULW with immediate offset and a source register operand.
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ulw $8, 0($9)
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# CHECK-BE: lwl $8, 0($9) # encoding: [0x89,0x28,0x00,0x00]
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# CHECK-BE: lwr $8, 3($9) # encoding: [0x99,0x28,0x00,0x03]
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# CHECK-LE: lwl $8, 3($9) # encoding: [0x03,0x00,0x28,0x89]
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# CHECK-LE: lwr $8, 0($9) # encoding: [0x00,0x00,0x28,0x99]
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ulw $8, 2($9)
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# CHECK-BE: lwl $8, 2($9) # encoding: [0x89,0x28,0x00,0x02]
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# CHECK-BE: lwr $8, 5($9) # encoding: [0x99,0x28,0x00,0x05]
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# CHECK-LE: lwl $8, 5($9) # encoding: [0x05,0x00,0x28,0x89]
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# CHECK-LE: lwr $8, 2($9) # encoding: [0x02,0x00,0x28,0x99]
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ulw $8, 0x8000($9)
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# CHECK-BE: ori $1, $zero, 32768 # encoding: [0x34,0x01,0x80,0x00]
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# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21]
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# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00]
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# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03]
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# CHECK-LE: ori $1, $zero, 32768 # encoding: [0x00,0x80,0x01,0x34]
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# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00]
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# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
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# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
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ulw $8, -0x8000($9)
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# CHECK-BE: lwl $8, -32768($9) # encoding: [0x89,0x28,0x80,0x00]
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# CHECK-BE: lwr $8, -32765($9) # encoding: [0x99,0x28,0x80,0x03]
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# CHECK-LE: lwl $8, -32765($9) # encoding: [0x03,0x80,0x28,0x89]
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# CHECK-LE: lwr $8, -32768($9) # encoding: [0x00,0x80,0x28,0x99]
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ulw $8, 0x10000($9)
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# CHECK-BE: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01]
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# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21]
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# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00]
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# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03]
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# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
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# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00]
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# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
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# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
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ulw $8, 0x18888($9)
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# CHECK-BE: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01]
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# CHECK-BE: ori $1, $1, 34952 # encoding: [0x34,0x21,0x88,0x88]
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# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21]
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# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00]
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# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03]
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# CHECK-LE: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
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# CHECK-LE: ori $1, $1, 34952 # encoding: [0x88,0x88,0x21,0x34]
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# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00]
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# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
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# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
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ulw $8, -32771($9)
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# CHECK-BE: lui $1, 65535 # encoding: [0x3c,0x01,0xff,0xff]
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# CHECK-BE: ori $1, $1, 32765 # encoding: [0x34,0x21,0x7f,0xfd]
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# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21]
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# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00]
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# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03]
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# CHECK-LE: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c]
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# CHECK-LE: ori $1, $1, 32765 # encoding: [0xfd,0x7f,0x21,0x34]
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# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00]
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# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
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# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
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ulw $8, 32765($9)
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# CHECK-BE: ori $1, $zero, 32765 # encoding: [0x34,0x01,0x7f,0xfd]
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# CHECK-BE: addu $1, $1, $9 # encoding: [0x00,0x29,0x08,0x21]
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# CHECK-BE: lwl $8, 0($1) # encoding: [0x88,0x28,0x00,0x00]
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# CHECK-BE: lwr $8, 3($1) # encoding: [0x98,0x28,0x00,0x03]
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# CHECK-LE: ori $1, $zero, 32765 # encoding: [0xfd,0x7f,0x01,0x34]
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# CHECK-LE: addu $1, $1, $9 # encoding: [0x21,0x08,0x29,0x00]
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# CHECK-LE: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
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# CHECK-LE: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
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1:
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add $4, $4, $4
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@ -369,3 +369,85 @@
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# CHECK: lbu $1, 0($1) # encoding: [0x00,0x00,0x21,0x90]
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# CHECK: sll $8, $8, 8 # encoding: [0x00,0x42,0x08,0x00]
|
||||
# CHECK: or $8, $8, $1 # encoding: [0x25,0x40,0x01,0x01]
|
||||
|
||||
# Test ulw with 64-bit immediate addresses.
|
||||
ulw $8, 0x100010001
|
||||
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
|
||||
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
|
||||
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
|
||||
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
|
||||
# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
|
||||
# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
|
||||
|
||||
ulw $8, 0x1000100010001
|
||||
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
|
||||
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
|
||||
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
|
||||
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
|
||||
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
|
||||
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
|
||||
# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
|
||||
# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
|
||||
|
||||
ulw $8, -0x100010001
|
||||
# CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c]
|
||||
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
|
||||
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
|
||||
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
|
||||
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
|
||||
# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34]
|
||||
# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
|
||||
# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
|
||||
|
||||
ulw $8, -0x1000100010001
|
||||
# CHECK: lui $1, 65534 # encoding: [0xfe,0xff,0x01,0x3c]
|
||||
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
|
||||
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
|
||||
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
|
||||
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
|
||||
# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34]
|
||||
# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
|
||||
# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
|
||||
|
||||
# Test ulw with source register and 64-bit immediate offset.
|
||||
ulw $8, 0x100010001($9)
|
||||
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
|
||||
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
|
||||
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
|
||||
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
|
||||
# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
|
||||
# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
|
||||
# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
|
||||
|
||||
ulw $8, 0x1000100010001($9)
|
||||
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
|
||||
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
|
||||
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
|
||||
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
|
||||
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
|
||||
# CHECK: ori $1, $1, 1 # encoding: [0x01,0x00,0x21,0x34]
|
||||
# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
|
||||
# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
|
||||
# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
|
||||
|
||||
ulw $8, -0x100010001($9)
|
||||
# CHECK: lui $1, 65535 # encoding: [0xff,0xff,0x01,0x3c]
|
||||
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
|
||||
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
|
||||
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
|
||||
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
|
||||
# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34]
|
||||
# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
|
||||
# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
|
||||
# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
|
||||
|
||||
ulw $8, -0x1000100010001($9)
|
||||
# CHECK: lui $1, 65534 # encoding: [0xfe,0xff,0x01,0x3c]
|
||||
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
|
||||
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
|
||||
# CHECK: ori $1, $1, 65534 # encoding: [0xfe,0xff,0x21,0x34]
|
||||
# CHECK: dsll $1, $1, 16 # encoding: [0x38,0x0c,0x01,0x00]
|
||||
# CHECK: ori $1, $1, 65535 # encoding: [0xff,0xff,0x21,0x34]
|
||||
# CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
|
||||
# CHECK: lwl $8, 3($1) # encoding: [0x03,0x00,0x28,0x88]
|
||||
# CHECK: lwr $8, 0($1) # encoding: [0x00,0x00,0x28,0x98]
|
||||
|
|
|
|||
|
|
@ -62,6 +62,11 @@
|
|||
|
||||
ulhu $5, 0
|
||||
|
||||
ulw $8, 2
|
||||
ulw $8, 0x8000
|
||||
ulw $8, 2($9)
|
||||
ulw $8, 0x8000($9)
|
||||
|
||||
add $4, $5, $6
|
||||
|
||||
.set noreorder
|
||||
|
|
@ -173,5 +178,14 @@
|
|||
ulhu $5, 0
|
||||
# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
|
||||
|
||||
ulw $8, 2
|
||||
# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
|
||||
ulw $8, 0x8000
|
||||
# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
|
||||
ulw $8, 2($9)
|
||||
# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
|
||||
ulw $8, 0x8000($9)
|
||||
# CHECK: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
|
||||
|
||||
add $4, $5, $6
|
||||
# CHECK-NOT: [[@LINE-1]]:3: warning: macro instruction expanded into multiple instructions
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user