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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
Add support for simple immediate handling to long instruction selection.
This allows us to handle code like 'add long %X, 123456789012' more efficiently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12683 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
ee98389808
commit
ab1d0e0963
@ -1718,76 +1718,88 @@ void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
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}
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// Special case: op Reg, <const>
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if (Class != cLong && isa<ConstantInt>(Op1)) {
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if (isa<ConstantInt>(Op1)) {
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ConstantInt *Op1C = cast<ConstantInt>(Op1);
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unsigned Op0r = getReg(Op0, MBB, IP);
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// xor X, -1 -> not X
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if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
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static unsigned const NOTTab[] = { X86::NOT8r, X86::NOT16r, X86::NOT32r };
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static unsigned const NOTTab[] = {
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X86::NOT8r, X86::NOT16r, X86::NOT32r, 0, X86::NOT32r
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};
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BuildMI(*MBB, IP, NOTTab[Class], 1, DestReg).addReg(Op0r);
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if (Class == cLong) // Invert the top part too
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BuildMI(*MBB, IP, X86::NOT32r, 1, DestReg+1).addReg(Op0r+1);
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return;
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}
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// add X, -1 -> dec X
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if (OperatorClass == 0 && Op1C->isAllOnesValue()) {
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static unsigned const DECTab[] = { X86::DEC8r, X86::DEC16r, X86::DEC32r };
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static unsigned const DECTab[] = {
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X86::DEC8r, X86::DEC16r, X86::DEC32r, 0, X86::DEC32r
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};
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BuildMI(*MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
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if (Class == cLong) // Dh = sbb Sh, 0
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BuildMI(*MBB, IP, X86::SBB32ri, 2, DestReg+1).addReg(Op0r+1).addImm(0);
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return;
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}
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// add X, 1 -> inc X
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if (OperatorClass == 0 && Op1C->equalsInt(1)) {
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static unsigned const INCTab[] = { X86::INC8r, X86::INC16r, X86::INC32r };
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static unsigned const INCTab[] = {
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X86::INC8r, X86::INC16r, X86::INC32r, 0, X86::INC32r
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};
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BuildMI(*MBB, IP, INCTab[Class], 1, DestReg).addReg(Op0r);
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if (Class == cLong) // Dh = adc Sh, 0
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BuildMI(*MBB, IP, X86::ADC32ri, 2, DestReg+1).addReg(Op0r+1).addImm(0);
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return;
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}
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static const unsigned OpcodeTab[][3] = {
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static const unsigned OpcodeTab[][5] = {
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// Arithmetic operators
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{ X86::ADD8ri, X86::ADD16ri, X86::ADD32ri }, // ADD
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{ X86::SUB8ri, X86::SUB16ri, X86::SUB32ri }, // SUB
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{ X86::ADD8ri, X86::ADD16ri, X86::ADD32ri, 0, X86::ADD32ri }, // ADD
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{ X86::SUB8ri, X86::SUB16ri, X86::SUB32ri, 0, X86::SUB32ri }, // SUB
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// Bitwise operators
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{ X86::AND8ri, X86::AND16ri, X86::AND32ri }, // AND
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{ X86:: OR8ri, X86:: OR16ri, X86:: OR32ri }, // OR
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{ X86::XOR8ri, X86::XOR16ri, X86::XOR32ri }, // XOR
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{ X86::AND8ri, X86::AND16ri, X86::AND32ri, 0, X86::AND32ri }, // AND
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{ X86:: OR8ri, X86:: OR16ri, X86:: OR32ri, 0, X86::OR32ri }, // OR
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{ X86::XOR8ri, X86::XOR16ri, X86::XOR32ri, 0, X86::XOR32ri }, // XOR
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};
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assert(Class < cFP && "General code handles 64-bit integer types!");
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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uint64_t Op1v = cast<ConstantInt>(Op1C)->getRawValue();
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BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1v);
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BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1v &0xFFFFFFFF);
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if (Class == cLong) {
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static const unsigned TopTab[] = {
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X86::ADC32ri, X86::SBB32ri, X86::AND32ri, X86::OR32ri, X86::XOR32ri
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};
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BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1)
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.addReg(Op0r+1).addImm(uint64_t(Op1v) >> 32);
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}
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return;
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}
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// Finally, handle the general case now.
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static const unsigned OpcodeTab[][4] = {
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// Arithmetic operators
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{ X86::ADD8rr, X86::ADD16rr, X86::ADD32rr, X86::FpADD }, // ADD
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{ X86::SUB8rr, X86::SUB16rr, X86::SUB32rr, X86::FpSUB }, // SUB
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{ X86::ADD8rr, X86::ADD16rr, X86::ADD32rr, X86::FpADD, X86::ADD32rr },// ADD
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{ X86::SUB8rr, X86::SUB16rr, X86::SUB32rr, X86::FpSUB, X86::SUB32rr },// SUB
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// Bitwise operators
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{ X86::AND8rr, X86::AND16rr, X86::AND32rr, 0 }, // AND
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{ X86:: OR8rr, X86:: OR16rr, X86:: OR32rr, 0 }, // OR
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{ X86::XOR8rr, X86::XOR16rr, X86::XOR32rr, 0 }, // XOR
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{ X86::AND8rr, X86::AND16rr, X86::AND32rr, 0, X86::AND32rr }, // AND
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{ X86:: OR8rr, X86:: OR16rr, X86:: OR32rr, 0, X86:: OR32rr }, // OR
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{ X86::XOR8rr, X86::XOR16rr, X86::XOR32rr, 0, X86::XOR32rr }, // XOR
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};
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bool isLong = false;
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if (Class == cLong) {
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isLong = true;
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Class = cInt; // Bottom 32 bits are handled just like ints
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}
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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assert(Opcode && "Floating point arguments to logical inst?");
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unsigned Op0r = getReg(Op0, MBB, IP);
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unsigned Op1r = getReg(Op1, MBB, IP);
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BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
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if (isLong) { // Handle the upper 32 bits of long values...
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if (Class == cLong) { // Handle the upper 32 bits of long values...
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static const unsigned TopTab[] = {
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X86::ADC32rr, X86::SBB32rr, X86::AND32rr, X86::OR32rr, X86::XOR32rr
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};
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@ -1718,76 +1718,88 @@ void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
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}
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// Special case: op Reg, <const>
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if (Class != cLong && isa<ConstantInt>(Op1)) {
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if (isa<ConstantInt>(Op1)) {
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ConstantInt *Op1C = cast<ConstantInt>(Op1);
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unsigned Op0r = getReg(Op0, MBB, IP);
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// xor X, -1 -> not X
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if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
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static unsigned const NOTTab[] = { X86::NOT8r, X86::NOT16r, X86::NOT32r };
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static unsigned const NOTTab[] = {
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X86::NOT8r, X86::NOT16r, X86::NOT32r, 0, X86::NOT32r
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};
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BuildMI(*MBB, IP, NOTTab[Class], 1, DestReg).addReg(Op0r);
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if (Class == cLong) // Invert the top part too
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BuildMI(*MBB, IP, X86::NOT32r, 1, DestReg+1).addReg(Op0r+1);
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return;
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}
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// add X, -1 -> dec X
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if (OperatorClass == 0 && Op1C->isAllOnesValue()) {
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static unsigned const DECTab[] = { X86::DEC8r, X86::DEC16r, X86::DEC32r };
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static unsigned const DECTab[] = {
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X86::DEC8r, X86::DEC16r, X86::DEC32r, 0, X86::DEC32r
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};
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BuildMI(*MBB, IP, DECTab[Class], 1, DestReg).addReg(Op0r);
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if (Class == cLong) // Dh = sbb Sh, 0
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BuildMI(*MBB, IP, X86::SBB32ri, 2, DestReg+1).addReg(Op0r+1).addImm(0);
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return;
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}
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// add X, 1 -> inc X
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if (OperatorClass == 0 && Op1C->equalsInt(1)) {
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static unsigned const INCTab[] = { X86::INC8r, X86::INC16r, X86::INC32r };
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static unsigned const INCTab[] = {
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X86::INC8r, X86::INC16r, X86::INC32r, 0, X86::INC32r
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};
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BuildMI(*MBB, IP, INCTab[Class], 1, DestReg).addReg(Op0r);
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if (Class == cLong) // Dh = adc Sh, 0
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BuildMI(*MBB, IP, X86::ADC32ri, 2, DestReg+1).addReg(Op0r+1).addImm(0);
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return;
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}
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static const unsigned OpcodeTab[][3] = {
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static const unsigned OpcodeTab[][5] = {
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// Arithmetic operators
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{ X86::ADD8ri, X86::ADD16ri, X86::ADD32ri }, // ADD
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{ X86::SUB8ri, X86::SUB16ri, X86::SUB32ri }, // SUB
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{ X86::ADD8ri, X86::ADD16ri, X86::ADD32ri, 0, X86::ADD32ri }, // ADD
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{ X86::SUB8ri, X86::SUB16ri, X86::SUB32ri, 0, X86::SUB32ri }, // SUB
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// Bitwise operators
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{ X86::AND8ri, X86::AND16ri, X86::AND32ri }, // AND
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{ X86:: OR8ri, X86:: OR16ri, X86:: OR32ri }, // OR
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{ X86::XOR8ri, X86::XOR16ri, X86::XOR32ri }, // XOR
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{ X86::AND8ri, X86::AND16ri, X86::AND32ri, 0, X86::AND32ri }, // AND
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{ X86:: OR8ri, X86:: OR16ri, X86:: OR32ri, 0, X86::OR32ri }, // OR
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{ X86::XOR8ri, X86::XOR16ri, X86::XOR32ri, 0, X86::XOR32ri }, // XOR
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};
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assert(Class < cFP && "General code handles 64-bit integer types!");
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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uint64_t Op1v = cast<ConstantInt>(Op1C)->getRawValue();
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BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1v);
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BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1v &0xFFFFFFFF);
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if (Class == cLong) {
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static const unsigned TopTab[] = {
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X86::ADC32ri, X86::SBB32ri, X86::AND32ri, X86::OR32ri, X86::XOR32ri
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};
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BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1)
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.addReg(Op0r+1).addImm(uint64_t(Op1v) >> 32);
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}
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return;
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}
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// Finally, handle the general case now.
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static const unsigned OpcodeTab[][4] = {
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// Arithmetic operators
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{ X86::ADD8rr, X86::ADD16rr, X86::ADD32rr, X86::FpADD }, // ADD
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{ X86::SUB8rr, X86::SUB16rr, X86::SUB32rr, X86::FpSUB }, // SUB
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{ X86::ADD8rr, X86::ADD16rr, X86::ADD32rr, X86::FpADD, X86::ADD32rr },// ADD
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{ X86::SUB8rr, X86::SUB16rr, X86::SUB32rr, X86::FpSUB, X86::SUB32rr },// SUB
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// Bitwise operators
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{ X86::AND8rr, X86::AND16rr, X86::AND32rr, 0 }, // AND
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{ X86:: OR8rr, X86:: OR16rr, X86:: OR32rr, 0 }, // OR
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{ X86::XOR8rr, X86::XOR16rr, X86::XOR32rr, 0 }, // XOR
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{ X86::AND8rr, X86::AND16rr, X86::AND32rr, 0, X86::AND32rr }, // AND
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{ X86:: OR8rr, X86:: OR16rr, X86:: OR32rr, 0, X86:: OR32rr }, // OR
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{ X86::XOR8rr, X86::XOR16rr, X86::XOR32rr, 0, X86::XOR32rr }, // XOR
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};
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bool isLong = false;
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if (Class == cLong) {
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isLong = true;
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Class = cInt; // Bottom 32 bits are handled just like ints
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}
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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assert(Opcode && "Floating point arguments to logical inst?");
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unsigned Op0r = getReg(Op0, MBB, IP);
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unsigned Op1r = getReg(Op1, MBB, IP);
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BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
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if (isLong) { // Handle the upper 32 bits of long values...
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if (Class == cLong) { // Handle the upper 32 bits of long values...
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static const unsigned TopTab[] = {
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X86::ADC32rr, X86::SBB32rr, X86::AND32rr, X86::OR32rr, X86::XOR32rr
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};
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