6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-19 06:31:18 +00:00
Code Issues Projects Releases Wiki Activity

Fix x86-64 encoding bug. REX prefix must always follow 0x0F prefix. For example, extractps in 64bit mode: 66 REX 0F 3A 17, not 66 0F 3A REX 17.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49157 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-04-03 08:53:17 +00:00
parent 90ce87b5bd
commit ab394bdcc0
1 changed files with 13 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
lib/Target/X86/X86CodeEmitter.cpp
View File

@ -558,16 +558,10 @@ void Emitter::emitInstruction(const MachineInstr &MI,
bool Need0FPrefix = false; bool Need0FPrefix = false;
switch (Desc->TSFlags & X86II::Op0Mask) { switch (Desc->TSFlags & X86II::Op0Mask) {
case X86II::TB: case X86II::TB: // Two-byte opcode prefix
Need0FPrefix = true; // Two-byte opcode prefix case X86II::T8: // 0F 38
break; case X86II::TA: // 0F 3A
case X86II::T8: Need0FPrefix = true;
MCE.emitByte(0x0F);
MCE.emitByte(0x38);
break;
case X86II::TA:
MCE.emitByte(0x0F);
MCE.emitByte(0x3A);
break; break;
case X86II::REP: break; // already handled. case X86II::REP: break; // already handled.
case X86II::XS: // F3 0F case X86II::XS: // F3 0F
@ -599,6 +593,15 @@ void Emitter::emitInstruction(const MachineInstr &MI,
if (Need0FPrefix) if (Need0FPrefix)
MCE.emitByte(0x0F); MCE.emitByte(0x0F);
switch (Desc->TSFlags & X86II::Op0Mask) {
case X86II::T8: // 0F 38
MCE.emitByte(0x38);
break;
case X86II::TA: // 0F 3A
MCE.emitByte(0x3A);
break;
}
// If this is a two-address instruction, skip one of the register operands. // If this is a two-address instruction, skip one of the register operands.
unsigned NumOps = Desc->getNumOperands(); unsigned NumOps = Desc->getNumOperands();
unsigned CurOp = 0; unsigned CurOp = 0;