diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 27a0e7b560d..f72713325ad 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -77,8 +77,8 @@ ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { static const unsigned DarwinCalleeSavedRegs[] = { // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved // register. - ARM::LR, ARM::R11, ARM::R10, ARM::R8, - ARM::R7, ARM::R6, ARM::R5, ARM::R4, + ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4, + ARM::R11, ARM::R10, ARM::R8, ARM::D15, ARM::D14, ARM::D13, ARM::D12, ARM::D11, ARM::D10, ARM::D9, ARM::D8, @@ -702,6 +702,7 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, bool LRSpilled = false; unsigned NumGPRSpills = 0; SmallVector UnspilledCS1GPRs; + SmallVector UnspilledCS2GPRs; ARMFunctionInfo *AFI = MF.getInfo(); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -768,7 +769,23 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, break; } } else { - UnspilledCS1GPRs.push_back(Reg); + if (!STI.isTargetDarwin()) { + UnspilledCS1GPRs.push_back(Reg); + continue; + } + + switch (Reg) { + case ARM::R4: + case ARM::R5: + case ARM::R6: + case ARM::R7: + case ARM::LR: + UnspilledCS1GPRs.push_back(Reg); + break; + default: + UnspilledCS2GPRs.push_back(Reg); + break; + } } } @@ -844,6 +861,13 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, break; } } + } else if (!UnspilledCS2GPRs.empty() && + !AFI->isThumb1OnlyFunction()) { + unsigned Reg = UnspilledCS2GPRs.front(); + MF.getRegInfo().setPhysRegUsed(Reg); + AFI->setCSRegisterIsSpilled(Reg); + if (!isReservedReg(MF, Reg)) + ExtraCSSpill = true; } } @@ -867,6 +891,17 @@ ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, NumExtras--; } } + // For non-Thumb1 functions, also check for hi-reg CS registers + if (!AFI->isThumb1OnlyFunction()) { + while (NumExtras && !UnspilledCS2GPRs.empty()) { + unsigned Reg = UnspilledCS2GPRs.back(); + UnspilledCS2GPRs.pop_back(); + if (!isReservedReg(MF, Reg)) { + Extras.push_back(Reg); + NumExtras--; + } + } + } if (Extras.size() && NumExtras == 0) { for (unsigned i = 0, e = Extras.size(); i != e; ++i) { MF.getRegInfo().setPhysRegUsed(Extras[i]); @@ -924,8 +959,10 @@ ARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF, FrameReg = ARM::SP; Offset += SPAdj; - if (AFI->isGPRCalleeSavedAreaFrame(FI)) - return Offset - AFI->getGPRCalleeSavedAreaOffset(); + if (AFI->isGPRCalleeSavedArea1Frame(FI)) + return Offset - AFI->getGPRCalleeSavedArea1Offset(); + else if (AFI->isGPRCalleeSavedArea2Frame(FI)) + return Offset - AFI->getGPRCalleeSavedArea2Offset(); else if (AFI->isDPRCalleeSavedAreaFrame(FI)) return Offset - AFI->getDPRCalleeSavedAreaOffset(); @@ -1623,7 +1660,8 @@ ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, } /// Move iterator past the next bunch of callee save load / store ops for -/// the particular spill area (1: integer area 1, 2: fp area, 0: don't care). +/// the particular spill area (1: integer area 1, 2: integer area 2, +/// 3: fp area, 0: don't care). static void movePastCSLoadStoreOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Opc1, int Opc2, unsigned Area, @@ -1636,13 +1674,15 @@ static void movePastCSLoadStoreOps(MachineBasicBlock &MBB, unsigned Category = 0; switch (MBBI->getOperand(0).getReg()) { case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7: - case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: case ARM::LR: Category = 1; break; + case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: + Category = STI.isTargetDarwin() ? 2 : 1; + break; case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11: case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15: - Category = 2; + Category = 3; break; default: Done = true; @@ -1672,7 +1712,7 @@ emitPrologue(MachineFunction &MF) const { // Determine the sizes of each callee-save spill areas and record which frame // belongs to which callee-save spill areas. - unsigned GPRCSSize = 0, DPRCSSize = 0; + unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; int FramePtrSpillFI = 0; // Allocate the vararg register save area. This is not counted in NumBytes. @@ -1693,15 +1733,25 @@ emitPrologue(MachineFunction &MF) const { case ARM::R5: case ARM::R6: case ARM::R7: + case ARM::LR: + if (Reg == FramePtr) + FramePtrSpillFI = FI; + AFI->addGPRCalleeSavedArea1Frame(FI); + GPRCS1Size += 4; + break; case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: - case ARM::LR: if (Reg == FramePtr) FramePtrSpillFI = FI; - AFI->addGPRCalleeSavedAreaFrame(FI); - GPRCSSize += 4; + if (STI.isTargetDarwin()) { + AFI->addGPRCalleeSavedArea2Frame(FI); + GPRCS2Size += 4; + } else { + AFI->addGPRCalleeSavedArea1Frame(FI); + GPRCS1Size += 4; + } break; default: AFI->addDPRCalleeSavedAreaFrame(FI); @@ -1709,11 +1759,15 @@ emitPrologue(MachineFunction &MF) const { } } - // Build the new SUBri to adjust SP for integer callee-save spill area. - emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCSSize); + // Build the new SUBri to adjust SP for integer callee-save spill area 1. + emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size); movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 1, STI); // Set FP to point to the stack slot that contains the previous FP. + // For Darwin, FP is R7, which has now been stored in spill area 1. + // Otherwise, if this is not Darwin, all the callee-saved registers go + // into spill area 1, including the FP in R11. In either case, it is + // now safe to emit this assignment. bool HasFP = hasFP(MF); if (HasFP) { unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri; @@ -1723,19 +1777,25 @@ emitPrologue(MachineFunction &MF) const { AddDefaultCC(AddDefaultPred(MIB)); } + // Build the new SUBri to adjust SP for integer callee-save spill area 2. + emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size); + // Build the new SUBri to adjust SP for FP callee-save spill area. + movePastCSLoadStoreOps(MBB, MBBI, ARM::STRi12, ARM::t2STRi12, 2, STI); emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize); // Determine starting offsets of spill areas. - unsigned DPRCSOffset = NumBytes - (GPRCSSize + DPRCSSize); - unsigned GPRCSOffset = DPRCSOffset + DPRCSSize; + unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); + unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; + unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; if (HasFP) AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); - AFI->setGPRCalleeSavedAreaOffset(GPRCSOffset); + AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); + AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); - movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 2, STI); + movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI); NumBytes = DPRCSOffset; if (NumBytes) { // Adjust SP after all the callee-save spills. @@ -1750,7 +1810,8 @@ emitPrologue(MachineFunction &MF) const { AFI->setShouldRestoreSPFromFP(true); } - AFI->setGPRCalleeSavedAreaSize(GPRCSSize); + AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); + AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); AFI->setDPRCalleeSavedAreaSize(DPRCSSize); // If we need dynamic stack realignment, do it here. Be paranoid and make @@ -1852,7 +1913,8 @@ emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { } // Move SP to start of FP callee save spill area. - NumBytes -= (AFI->getGPRCalleeSavedAreaSize() + + NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + + AFI->getGPRCalleeSavedArea2Size() + AFI->getDPRCalleeSavedAreaSize()); // Reset SP based on frame pointer only if the stack frame extends beyond @@ -1878,13 +1940,17 @@ emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { } else if (NumBytes) emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); - // Move SP to start of integer callee save spill area. - movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 2, STI); + // Move SP to start of integer callee save spill area 2. + movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI); emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize()); + // Move SP to start of integer callee save spill area 1. + movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 2, STI); + emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size()); + // Move SP to SP upon entry to the function. movePastCSLoadStoreOps(MBB, MBBI, ARM::LDRi12, ARM::t2LDRi12, 1, STI); - emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedAreaSize()); + emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size()); } if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND || diff --git a/lib/Target/ARM/ARMMachineFunctionInfo.h b/lib/Target/ARM/ARMMachineFunctionInfo.h index 3b34a23774d..514c26b4daf 100644 --- a/lib/Target/ARM/ARMMachineFunctionInfo.h +++ b/lib/Target/ARM/ARMMachineFunctionInfo.h @@ -55,22 +55,28 @@ class ARMFunctionInfo : public MachineFunctionInfo { /// spill stack offset. unsigned FramePtrSpillOffset; - /// GPRCSOffset, DPRCSOffset - Starting offset of callee saved register - /// spills areas (excluding R9 for Mac OS X): + /// GPRCS1Offset, GPRCS2Offset, DPRCSOffset - Starting offset of callee saved + /// register spills areas. For Mac OS X: /// - /// GPR callee-saved (1) : r4, r5, r6, r7, r8, r9, r10, r11, lr + /// GPR callee-saved (1) : r4, r5, r6, r7, lr + /// -------------------------------------------- + /// GPR callee-saved (2) : r8, r10, r11 /// -------------------------------------------- /// DPR callee-saved : d8 - d15 - unsigned GPRCSOffset; + unsigned GPRCS1Offset; + unsigned GPRCS2Offset; unsigned DPRCSOffset; - /// GPRCSSize, DPRCSSize - Sizes of callee saved register spills areas. - unsigned GPRCSSize; + /// GPRCS1Size, GPRCS2Size, DPRCSSize - Sizes of callee saved register spills + /// areas. + unsigned GPRCS1Size; + unsigned GPRCS2Size; unsigned DPRCSSize; - /// GPRCSFrames, DPRCSFrames - Keeps track of frame indices which belong - /// to these spill areas. - BitVector GPRCSFrames; + /// GPRCS1Frames, GPRCS2Frames, DPRCSFrames - Keeps track of frame indices + /// which belong to these spill areas. + BitVector GPRCS1Frames; + BitVector GPRCS2Frames; BitVector DPRCSFrames; /// SpilledCSRegs - A BitVector mask of all spilled callee-saved registers. @@ -95,9 +101,9 @@ public: hasThumb2(false), VarArgsRegSaveSize(0), HasStackFrame(false), RestoreSPFromFP(false), LRSpilledForFarJump(false), - FramePtrSpillOffset(0), GPRCSOffset(0), DPRCSOffset(0), - GPRCSSize(0), DPRCSSize(0), - GPRCSFrames(0), DPRCSFrames(0), + FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0), + GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0), + GPRCS1Frames(0), GPRCS2Frames(0), DPRCSFrames(0), JumpTableUId(0), ConstPoolEntryUId(0), VarArgsFrameIndex(0), HasITBlocks(false) {} @@ -106,9 +112,9 @@ public: hasThumb2(MF.getTarget().getSubtarget().hasThumb2()), VarArgsRegSaveSize(0), HasStackFrame(false), RestoreSPFromFP(false), LRSpilledForFarJump(false), - FramePtrSpillOffset(0), GPRCSOffset(0), DPRCSOffset(0), - GPRCSSize(0), DPRCSSize(0), - GPRCSFrames(32), DPRCSFrames(32), + FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0), + GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0), + GPRCS1Frames(32), GPRCS2Frames(32), DPRCSFrames(32), SpilledCSRegs(MF.getTarget().getRegisterInfo()->getNumRegs()), JumpTableUId(0), ConstPoolEntryUId(0), VarArgsFrameIndex(0), HasITBlocks(false) {} @@ -132,22 +138,31 @@ public: unsigned getFramePtrSpillOffset() const { return FramePtrSpillOffset; } void setFramePtrSpillOffset(unsigned o) { FramePtrSpillOffset = o; } - unsigned getGPRCalleeSavedAreaOffset() const { return GPRCSOffset; } + unsigned getGPRCalleeSavedArea1Offset() const { return GPRCS1Offset; } + unsigned getGPRCalleeSavedArea2Offset() const { return GPRCS2Offset; } unsigned getDPRCalleeSavedAreaOffset() const { return DPRCSOffset; } - void setGPRCalleeSavedAreaOffset(unsigned o) { GPRCSOffset = o; } + void setGPRCalleeSavedArea1Offset(unsigned o) { GPRCS1Offset = o; } + void setGPRCalleeSavedArea2Offset(unsigned o) { GPRCS2Offset = o; } void setDPRCalleeSavedAreaOffset(unsigned o) { DPRCSOffset = o; } - unsigned getGPRCalleeSavedAreaSize() const { return GPRCSSize; } + unsigned getGPRCalleeSavedArea1Size() const { return GPRCS1Size; } + unsigned getGPRCalleeSavedArea2Size() const { return GPRCS2Size; } unsigned getDPRCalleeSavedAreaSize() const { return DPRCSSize; } - void setGPRCalleeSavedAreaSize(unsigned s) { GPRCSSize = s; } + void setGPRCalleeSavedArea1Size(unsigned s) { GPRCS1Size = s; } + void setGPRCalleeSavedArea2Size(unsigned s) { GPRCS2Size = s; } void setDPRCalleeSavedAreaSize(unsigned s) { DPRCSSize = s; } - bool isGPRCalleeSavedAreaFrame(int fi) const { - if (fi < 0 || fi >= (int)GPRCSFrames.size()) + bool isGPRCalleeSavedArea1Frame(int fi) const { + if (fi < 0 || fi >= (int)GPRCS1Frames.size()) return false; - return GPRCSFrames[fi]; + return GPRCS1Frames[fi]; + } + bool isGPRCalleeSavedArea2Frame(int fi) const { + if (fi < 0 || fi >= (int)GPRCS2Frames.size()) + return false; + return GPRCS2Frames[fi]; } bool isDPRCalleeSavedAreaFrame(int fi) const { if (fi < 0 || fi >= (int)DPRCSFrames.size()) @@ -155,16 +170,28 @@ public: return DPRCSFrames[fi]; } - void addGPRCalleeSavedAreaFrame(int fi) { + void addGPRCalleeSavedArea1Frame(int fi) { if (fi >= 0) { - int Size = GPRCSFrames.size(); + int Size = GPRCS1Frames.size(); if (fi >= Size) { Size *= 2; if (fi >= Size) Size = fi+1; - GPRCSFrames.resize(Size); + GPRCS1Frames.resize(Size); } - GPRCSFrames[fi] = true; + GPRCS1Frames[fi] = true; + } + } + void addGPRCalleeSavedArea2Frame(int fi) { + if (fi >= 0) { + int Size = GPRCS2Frames.size(); + if (fi >= Size) { + Size *= 2; + if (fi >= Size) + Size = fi+1; + GPRCS2Frames.resize(Size); + } + GPRCS2Frames[fi] = true; } } void addDPRCalleeSavedAreaFrame(int fi) { diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp index 5c9fa704a7c..cd8ea434539 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -596,8 +596,10 @@ Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + MF.getFrameInfo()->getStackSize() + SPAdj; - if (AFI->isGPRCalleeSavedAreaFrame(FrameIndex)) - Offset -= AFI->getGPRCalleeSavedAreaOffset(); + if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex)) + Offset -= AFI->getGPRCalleeSavedArea1Offset(); + else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) + Offset -= AFI->getGPRCalleeSavedArea2Offset(); else if (MF.getFrameInfo()->hasVarSizedObjects()) { assert(SPAdj == 0 && hasFP(MF) && "Unexpected"); // There are alloca()'s in this function, must reference off the frame @@ -706,7 +708,7 @@ void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const { // Determine the sizes of each callee-save spill areas and record which frame // belongs to which callee-save spill areas. - unsigned GPRCSSize = 0, DPRCSSize = 0; + unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; int FramePtrSpillFI = 0; if (VARegSaveSize) @@ -726,15 +728,25 @@ void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const { case ARM::R5: case ARM::R6: case ARM::R7: + case ARM::LR: + if (Reg == FramePtr) + FramePtrSpillFI = FI; + AFI->addGPRCalleeSavedArea1Frame(FI); + GPRCS1Size += 4; + break; case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11: - case ARM::LR: if (Reg == FramePtr) FramePtrSpillFI = FI; - AFI->addGPRCalleeSavedAreaFrame(FI); - GPRCSSize += 4; + if (STI.isTargetDarwin()) { + AFI->addGPRCalleeSavedArea2Frame(FI); + GPRCS2Size += 4; + } else { + AFI->addGPRCalleeSavedArea1Frame(FI); + GPRCS1Size += 4; + } break; default: AFI->addDPRCalleeSavedAreaFrame(FI); @@ -756,10 +768,12 @@ void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const { } // Determine starting offsets of spill areas. - unsigned DPRCSOffset = NumBytes - (GPRCSSize + DPRCSSize); - unsigned GPRCSOffset = DPRCSOffset + DPRCSSize; + unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); + unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; + unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); - AFI->setGPRCalleeSavedAreaOffset(GPRCSOffset); + AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); + AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); NumBytes = DPRCSOffset; @@ -772,7 +786,8 @@ void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const { MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - AFI->getFramePtrSpillOffset()); - AFI->setGPRCalleeSavedAreaSize(GPRCSSize); + AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); + AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); AFI->setDPRCalleeSavedAreaSize(DPRCSSize); // If we need a base pointer, set it up here. It's whatever the value @@ -833,7 +848,8 @@ void Thumb1RegisterInfo::emitEpilogue(MachineFunction &MF, } // Move SP to start of FP callee save spill area. - NumBytes -= (AFI->getGPRCalleeSavedAreaSize() + + NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + + AFI->getGPRCalleeSavedArea2Size() + AFI->getDPRCalleeSavedAreaSize()); if (AFI->shouldRestoreSPFromFP()) { diff --git a/test/CodeGen/ARM/lsr-code-insertion.ll b/test/CodeGen/ARM/lsr-code-insertion.ll index 9f1a44a5feb..b8c543b1bd1 100644 --- a/test/CodeGen/ARM/lsr-code-insertion.ll +++ b/test/CodeGen/ARM/lsr-code-insertion.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -stats |& grep {36.*Number of machine instrs printed} +; RUN: llc < %s -stats |& grep {38.*Number of machine instrs printed} ; RUN: llc < %s -stats |& not grep {.*Number of re-materialization} ; This test really wants to check that the resultant "cond_true" block only ; has a single store in it, and that cond_true55 only has code to materialize diff --git a/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll b/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll index a0caf3b76a1..f91e1c9febe 100644 --- a/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll +++ b/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll @@ -32,14 +32,15 @@ define fastcc i32 @parse_percent_token() nounwind { entry: -; CHECK: itt eq -; CHECK: itt eq -; CHECK: itt eq -; CHECK: itt eq -; CHECK: itt eq +; CHECK: ittt eq +; CHECK: ittt eq +; CHECK: ittt eq +; CHECK: ittt eq +; CHECK: ittt eq ; CHECK: moveq r0 ; CHECK-NOT: LBB0_ -; CHECK: ldmiaeq +; CHECK: ldreq +; CHECK: popeq switch i32 undef, label %bb7 [ i32 37, label %bb43 i32 48, label %bb5 diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp index a7b96564799..fbe9947b096 100644 --- a/utils/TableGen/CodeEmitterGen.cpp +++ b/utils/TableGen/CodeEmitterGen.cpp @@ -17,9 +17,15 @@ #include "CodeGenTarget.h" #include "Record.h" #include "llvm/ADT/StringExtras.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" using namespace llvm; +static cl::opt +MCEmitter("mc-code-emitter", + cl::desc("Generate CodeEmitter for use with the MC library."), + cl::init(false)); + void CodeEmitterGen::reverseBits(std::vector &Insts) { for (std::vector::iterator I = Insts.begin(), E = Insts.end(); I != E; ++I) {