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Baby steps towards ARM fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109047 91177308-0d34-0410-b5e6-96231b3b80d8
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lib/Target/ARM/ARMFastISel.cpp
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71
lib/Target/ARM/ARMFastISel.cpp
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//===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the ARM-specific support for the FastISel class. Some
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// of the target-specific code is generated by tablegen in the file
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// ARMGenFastISel.inc, which is #included here.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMRegisterInfo.h"
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#include "ARMTargetMachine.h"
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#include "ARMSubtarget.h"
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#include "llvm/CallingConv.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/GlobalVariable.h"
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#include "llvm/Instructions.h"
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#include "llvm/IntrinsicInst.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/FunctionLoweringInfo.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/CallSite.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/GetElementPtrTypeIterator.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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namespace {
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class ARMFastISel : public FastISel {
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/// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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const ARMSubtarget *Subtarget;
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public:
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explicit ARMFastISel(FunctionLoweringInfo &funcInfo) : FastISel(funcInfo) {
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Subtarget = &TM.getSubtarget<ARMSubtarget>();
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}
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virtual bool TargetSelectInstruction(const Instruction *I);
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#include "ARMGenFastISel.inc"
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};
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} // end anonymous namespace
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// #include "ARMGenCallingConv.inc"
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bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
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switch (I->getOpcode()) {
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default: break;
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}
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return false;
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}
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namespace llvm {
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llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
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return new ARMFastISel(funcInfo);
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}
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}
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@ -694,6 +694,12 @@ TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
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return TargetLowering::getRegClassFor(VT);
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}
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// Create a fast isel object.
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FastISel *
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ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
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return ARM::createFastISel(funcInfo);
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}
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/// getFunctionAlignment - Return the Log2 alignment of this function.
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unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
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return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
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@ -17,6 +17,7 @@
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#include "ARMSubtarget.h"
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include <vector>
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@ -261,6 +262,10 @@ namespace llvm {
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/// getFunctionAlignment - Return the Log2 alignment of this function.
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virtual unsigned getFunctionAlignment(const Function *F) const;
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/// createFastISel - This method returns a target specific FastISel object,
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/// or null if the target does not support "fast" ISel.
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virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
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Sched::Preference getSchedulingPreference(SDNode *N) const;
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bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
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@ -387,6 +392,10 @@ namespace llvm {
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unsigned BinOpcode) const;
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};
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namespace ARM {
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FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
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}
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}
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#endif // ARMISELLOWERING_H
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@ -11,6 +11,7 @@ tablegen(ARMGenDAGISel.inc -gen-dag-isel)
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tablegen(ARMGenCallingConv.inc -gen-callingconv)
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tablegen(ARMGenSubtarget.inc -gen-subtarget)
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tablegen(ARMGenEDInfo.inc -gen-enhanced-disassembly-info)
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tablegen(ARMFastISel.inc -gen-fast-isel)
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add_llvm_target(ARMCodeGen
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ARMAsmPrinter.cpp
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@ -17,7 +17,8 @@ BUILT_SOURCES = ARMGenRegisterInfo.h.inc ARMGenRegisterNames.inc \
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ARMGenInstrInfo.inc ARMGenAsmWriter.inc \
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ARMGenDAGISel.inc ARMGenSubtarget.inc \
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ARMGenCodeEmitter.inc ARMGenCallingConv.inc \
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ARMGenDecoderTables.inc ARMGenEDInfo.inc
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ARMGenDecoderTables.inc ARMGenEDInfo.inc \
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ARMGenFastISel.inc
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DIRS = AsmPrinter AsmParser Disassembler TargetInfo
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15
test/CodeGen/ARM/fast-isel.ll
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15
test/CodeGen/ARM/fast-isel.ll
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; RUN: llc < %s -fast-isel -fast-isel-abort -march=arm
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; Very basic fast-isel functionality.
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define i32 @add(i32 %a, i32 %b) nounwind ssp {
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entry:
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%a.addr = alloca i32, align 4
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%b.addr = alloca i32, align 4
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store i32 %a, i32* %a.addr
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store i32 %b, i32* %b.addr
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%tmp = load i32* %a.addr
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%tmp1 = load i32* %b.addr
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%add = add nsw i32 %tmp, %tmp1
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ret i32 %add
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}
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