6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-14 11:32:34 +00:00
Code Issues Projects Releases Wiki Activity

[mips] Remove unnecessary predicates.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169577 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-12-07 03:01:24 +00:00
parent 70d3bebc8b
commit ab9705f8fa
3 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -66,7 +66,7 @@ multiclass AtomicCmpSwap64<PatFrag Op, string Width> {
}
}
}
let usesCustomInserter = 1, Predicates = [HasMips64, HasStandardEncoding],
let usesCustomInserter = 1, Predicates = [HasStandardEncoding],
DecoderNamespace = "Mips64" in {
defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64, "load_add_64">;
defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64, "load_sub_64">;

4
lib/Target/Mips/MipsCondMov.td
View File

@ -107,7 +107,7 @@ multiclass MovnPats<RegisterClass CRC, RegisterClass DRC, Instruction MOVNInst,
// Instantiation of instructions.
def MOVZ_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0a, "movz">;
let Predicates = [HasMips64, HasStandardEncoding],
let Predicates = [HasStandardEncoding],
DecoderNamespace = "Mips64" in {
def MOVZ_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0a, "movz">;
def MOVZ_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0a, "movz"> {
@ -119,7 +119,7 @@ let Predicates = [HasMips64, HasStandardEncoding],
}
def MOVN_I_I : CondMovIntInt<CPURegs, CPURegs, 0x0b, "movn">;
let Predicates = [HasMips64, HasStandardEncoding],
let Predicates = [HasStandardEncoding],
DecoderNamespace = "Mips64" in {
def MOVN_I_I64 : CondMovIntInt<CPURegs, CPU64Regs, 0x0b, "movn">;
def MOVN_I64_I : CondMovIntInt<CPU64Regs, CPURegs, 0x0b, "movn"> {

2
lib/Target/Mips/MipsInstrInfo.td
View File

@ -1084,7 +1084,7 @@ def MSUBU : MArithR<5, "msubu", MipsMSubu>;
// MUL is a assembly macro in the current used ISAs. In recent ISA's
// it is a real instruction.
def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
Requires<[HasMips32, HasStandardEncoding]>;
Requires<[HasStandardEncoding]>;
def RDHWR : ReadHardware<CPURegs, HWRegs>;