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Throw the switch to allow FastISel to emit instructions whose return types different from their inputs. Next step: adding lowering pattens in FastISel that actually use these newly available opcodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55349 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -62,14 +62,15 @@ struct OperandsSignature {
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///
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///
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bool initialize(TreePatternNode *InstPatNode,
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bool initialize(TreePatternNode *InstPatNode,
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const CodeGenTarget &Target,
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const CodeGenTarget &Target,
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MVT::SimpleValueType VT,
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MVT::SimpleValueType VT) {
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const CodeGenRegisterClass *DstRC) {
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if (!InstPatNode->isLeaf() &&
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if (!InstPatNode->isLeaf() &&
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InstPatNode->getOperator()->getName() == "imm") {
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InstPatNode->getOperator()->getName() == "imm") {
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Operands.push_back("i");
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Operands.push_back("i");
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return true;
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return true;
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}
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}
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const CodeGenRegisterClass *DstRC = 0;
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for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
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for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) {
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TreePatternNode *Op = InstPatNode->getChild(i);
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TreePatternNode *Op = InstPatNode->getChild(i);
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// For now, filter out any operand with a predicate.
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// For now, filter out any operand with a predicate.
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@ -105,8 +106,11 @@ struct OperandsSignature {
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if (!RC)
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if (!RC)
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return false;
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return false;
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// For now, all the operands must have the same register class.
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// For now, all the operands must have the same register class.
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if (DstRC) {
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if (DstRC != RC)
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if (DstRC != RC)
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return false;
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return false;
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} else
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DstRC = RC;
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Operands.push_back("r");
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Operands.push_back("r");
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}
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}
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return true;
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return true;
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@ -220,7 +224,10 @@ void FastISelEmitter::run(std::ostream &OS) {
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Record *InstPatOp = InstPatNode->getOperator();
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Record *InstPatOp = InstPatNode->getOperator();
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std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
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std::string OpcodeName = getOpcodeName(InstPatOp, CGP);
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MVT::SimpleValueType VT = InstPatNode->getTypeNum(0);
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MVT::SimpleValueType RetVT = InstPatNode->getTypeNum(0);
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MVT::SimpleValueType VT = RetVT;
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if (InstPatNode->getNumChildren())
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VT = InstPatNode->getChild(0)->getTypeNum(0);
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// For now, filter out instructions which just set a register to
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// For now, filter out instructions which just set a register to
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// an Operand or an immediate, like MOV32ri.
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// an Operand or an immediate, like MOV32ri.
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@ -233,7 +240,7 @@ void FastISelEmitter::run(std::ostream &OS) {
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// Check all the operands.
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// Check all the operands.
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OperandsSignature Operands;
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OperandsSignature Operands;
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if (!Operands.initialize(InstPatNode, Target, VT, DstRC))
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if (!Operands.initialize(InstPatNode, Target, VT))
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continue;
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continue;
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// Get the predicate that guards this pattern.
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// Get the predicate that guards this pattern.
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@ -244,9 +251,9 @@ void FastISelEmitter::run(std::ostream &OS) {
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Pattern.getDstPattern()->getOperator()->getName(),
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Pattern.getDstPattern()->getOperator()->getName(),
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DstRC
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DstRC
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};
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};
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assert(!SimplePatterns[Operands][OpcodeName][VT][VT].count(PredicateCheck) &&
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assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) &&
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"Duplicate pattern!");
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"Duplicate pattern!");
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SimplePatterns[Operands][OpcodeName][VT][VT][PredicateCheck] = Memo;
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SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo;
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}
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}
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// Declare the target FastISel class.
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// Declare the target FastISel class.
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@ -398,7 +405,7 @@ void FastISelEmitter::run(std::ostream &OS) {
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// Emit one function for the type that demultiplexes on return type.
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// Emit one function for the type that demultiplexes on return type.
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OS << "unsigned FastISel::FastEmit_"
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OS << "unsigned FastISel::FastEmit_"
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<< getLegalCName(Opcode) << "_"
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<< getLegalCName(Opcode) << "_"
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<< getLegalCName(getName(VT));
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<< getLegalCName(getName(VT)) << "_";
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Operands.PrintManglingSuffix(OS);
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Operands.PrintManglingSuffix(OS);
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OS << "(MVT::SimpleValueType RetVT";
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OS << "(MVT::SimpleValueType RetVT";
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if (!Operands.empty())
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if (!Operands.empty())
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