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R600/SI: Move PHIs that define SGPRs to the VALU in most cases
This fixes a bug that is uncovered by a future commit and will be tested by the test/CodeGen/R600/sgpr-control-flow.ll test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218352 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -238,14 +238,66 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
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// If a PHI node defines an SGPR and any of its operands are VGPRs,
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// then we need to move it to the VALU.
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//
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// Also, if a PHI node defines an SGPR and has all SGPR operands
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// we must move it to the VALU, because the SGPR operands will
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// all end up being assigned the same register, which means
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// there is a potential for a conflict if different threads take
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// different control flow paths.
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//
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// For Example:
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//
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// sgpr0 = def;
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// ...
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// sgpr1 = def;
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// ...
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// sgpr2 = PHI sgpr0, sgpr1
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// use sgpr2;
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//
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// Will Become:
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//
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// sgpr2 = def;
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// ...
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// sgpr2 = def;
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// ...
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// use sgpr2
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//
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// FIXME: This is OK if the branching decision is made based on an
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// SGPR value.
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bool SGPRBranch = false;
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// The one exception to this rule is when one of the operands
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// is defined by a SI_BREAK, SI_IF_BREAK, or SI_ELSE_BREAK
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// instruction. In this case, there we know the program will
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// never enter the second block (the loop) without entering
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// the first block (where the condition is computed), so there
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// is no chance for values to be over-written.
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bool HasBreakDef = false;
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for (unsigned i = 1; i < MI.getNumOperands(); i+=2) {
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unsigned Reg = MI.getOperand(i).getReg();
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if (TRI->hasVGPRs(MRI.getRegClass(Reg))) {
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TII->moveToVALU(MI);
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break;
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}
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MachineInstr *DefInstr = MRI.getUniqueVRegDef(Reg);
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assert(DefInstr);
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switch(DefInstr->getOpcode()) {
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case AMDGPU::SI_BREAK:
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case AMDGPU::SI_IF_BREAK:
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case AMDGPU::SI_ELSE_BREAK:
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// If we see a PHI instruction that defines an SGPR, then that PHI
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// instruction has already been considered and should have
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// a *_BREAK as an operand.
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case AMDGPU::PHI:
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HasBreakDef = true;
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break;
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}
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}
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if (!SGPRBranch && !HasBreakDef)
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TII->moveToVALU(MI);
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break;
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}
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case AMDGPU::REG_SEQUENCE: {
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