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DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegClass. Add two test cases.

Browse Source 
rdar://problem/9182892


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128299 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-03-25 19:35:37 +00:00
parent b66a097612
commit abeea57639
2 changed files with 9 additions and 2 deletions
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5
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
View File

@ -1868,7 +1868,7 @@ static bool DisassembleThumb2LdSt(bool Load, MCInst &MI, unsigned Opcode,
OpInfo[1].RegClass == ARM::GPRRegClassID &&
"Expect >= 3 operands and first two as reg operands");
bool ThreeReg = (OpInfo[2].RegClass == ARM::GPRRegClassID);
bool ThreeReg = (OpInfo[2].RegClass > 0);
bool TIED_TO = ThreeReg && TID.getOperandConstraint(2, TOI::TIED_TO) != -1;
bool Imm12 = !ThreeReg && slice(insn, 23, 23) == 1; // ARMInstrThumb2.td
@ -1912,7 +1912,8 @@ static bool DisassembleThumb2LdSt(bool Load, MCInst &MI, unsigned Opcode,
++OpIdx;
if (ThreeReg) {
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
// This could be an offset register or a TIED_TO register.
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B,OpInfo[OpIdx].RegClass,
R2)));
++OpIdx;
}

6
test/MC/Disassembler/ARM/thumb-tests.txt
View File

@ -166,3 +166,9 @@
# CHECK: tbb [r5, r4]
0xd5 0xe8 0x04 0xf0
# CHECK: ldr.w r4, [sp, r4, lsl #3]
0x5d 0xf8 0x34 0x40
# CHECK: ldr.w r5, [r6, #30]
0x56 0xf8 0x1e 0x56