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Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89542 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-11-21 06:21:52 +00:00
parent e54cb16308
commit ac0869dc8a
6 changed files with 414 additions and 297 deletions
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47
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -39,6 +39,10 @@ static cl::opt<bool>
EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
cl::desc("Enable ARM 2-addr to 3-addr conv"));
static cl::opt<bool>
PredicateNEON("predicate-neon", cl::Hidden,
cl::desc("Allow NEON instructions to be predicated"));
ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
: TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
Subtarget(STI) {
@ -402,6 +406,21 @@ bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
return Found;
}
/// isPredicable - Return true if the specified instruction can be predicated.
/// By default, this returns true for every instruction with a
/// PredicateOperand.
bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
const TargetInstrDesc &TID = MI->getDesc();
if (!TID.isPredicable())
return false;
if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) {
ARMFunctionInfo *AFI =
MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
return PredicateNEON && AFI->isThumb2Function();
}
return true;
}
/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
@ -647,11 +666,13 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
SrcRC == ARM::DPR_VFP2RegisterClass ||
SrcRC == ARM::DPR_8RegisterClass) {
// Always use neon reg-reg move if source or dest is NEON-only regclass.
BuildMI(MBB, I, DL, get(ARM::VMOVDneon), DestReg).addReg(SrcReg);
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVDneon),
DestReg).addReg(SrcReg));
} else if (DestRC == ARM::QPRRegisterClass ||
DestRC == ARM::QPR_VFP2RegisterClass ||
DestRC == ARM::QPR_8RegisterClass) {
BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVQ),
DestReg).addReg(SrcReg));
} else {
return false;
}
@ -695,13 +716,14 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
// FIXME: Neon instructions should support predicates
if (Align >= 16
&& (getRegisterInfo().needsStackRealignment(MF))) {
BuildMI(MBB, I, DL, get(ARM::VST1q64))
.addFrameIndex(FI).addImm(0).addImm(0).addImm(128).addMemOperand(MMO)
.addReg(SrcReg, getKillRegState(isKill));
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
.addFrameIndex(FI).addImm(0).addImm(0).addImm(128)
.addMemOperand(MMO)
.addReg(SrcReg, getKillRegState(isKill)));
} else {
BuildMI(MBB, I, DL, get(ARM::VSTRQ)).
addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRQ)).
addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
}
}
}
@ -740,11 +762,12 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
// FIXME: Neon instructions should support predicates
if (Align >= 16
&& (getRegisterInfo().needsStackRealignment(MF))) {
BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
.addFrameIndex(FI).addImm(0).addImm(0).addImm(128).addMemOperand(MMO);
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
.addFrameIndex(FI).addImm(0).addImm(0).addImm(128)
.addMemOperand(MMO));
} else {
BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0).
addMemOperand(MMO);
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg)
.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
}
}
}

2
lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -220,6 +220,8 @@ public:
virtual bool DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const;
virtual bool isPredicable(MachineInstr *MI) const;
/// GetInstSize - Returns the size of the specified MachineInstr.
///
virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;

73
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -1049,12 +1049,15 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDValue Op, unsigned NumVecs,
case MVT::v4i32: OpcodeIndex = 2; break;
}
SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
if (is64BitVector) {
unsigned Opc = DOpcodes[OpcodeIndex];
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align, Chain };
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align,
Pred, PredReg, Chain };
std::vector<EVT> ResTys(NumVecs, VT);
ResTys.push_back(MVT::Other);
return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5);
return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 7);
}
EVT RegVT = GetNEONSubregVT(VT);
@ -1062,10 +1065,11 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDValue Op, unsigned NumVecs,
// Quad registers are directly supported for VLD2,
// loading 2 pairs of D regs.
unsigned Opc = QOpcodes0[OpcodeIndex];
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align, Chain };
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align,
Pred, PredReg, Chain };
std::vector<EVT> ResTys(4, VT);
ResTys.push_back(MVT::Other);
SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5);
SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 7);
Chain = SDValue(VLd, 4);
// Combine the even and odd subregs to produce the result.
@ -1086,15 +1090,16 @@ SDNode *ARMDAGToDAGISel::SelectVLD(SDValue Op, unsigned NumVecs,
// Load the even subregs.
unsigned Opc = QOpcodes0[OpcodeIndex];
const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Align, Chain };
SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 5);
const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Align,
Pred, PredReg, Chain };
SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 7);
Chain = SDValue(VLdA, NumVecs+1);
// Load the odd subregs.
Opc = QOpcodes1[OpcodeIndex];
const SDValue OpsB[] = { SDValue(VLdA, NumVecs), MemUpdate, MemOpc,
Align, Chain };
SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 5);
Align, Pred, PredReg, Chain };
SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 7);
Chain = SDValue(VLdB, NumVecs+1);
// Combine the even and odd subregs to produce the result.
@ -1138,6 +1143,9 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDValue Op, unsigned NumVecs,
case MVT::v4i32: OpcodeIndex = 2; break;
}
SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SmallVector<SDValue, 8> Ops;
Ops.push_back(MemAddr);
Ops.push_back(MemUpdate);
@ -1148,8 +1156,10 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDValue Op, unsigned NumVecs,
unsigned Opc = DOpcodes[OpcodeIndex];
for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
Ops.push_back(N->getOperand(Vec+3));
Ops.push_back(Pred);
Ops.push_back(PredReg);
Ops.push_back(Chain);
return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+5);
return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+7);
}
EVT RegVT = GetNEONSubregVT(VT);
@ -1163,8 +1173,10 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDValue Op, unsigned NumVecs,
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
N->getOperand(Vec+3)));
}
Ops.push_back(Pred);
Ops.push_back(PredReg);
Ops.push_back(Chain);
return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 9);
return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 11);
}
// Otherwise, quad registers are stored with two separate instructions,
@ -1177,10 +1189,12 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDValue Op, unsigned NumVecs,
for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
N->getOperand(Vec+3)));
Ops.push_back(Pred);
Ops.push_back(PredReg);
Ops.push_back(Chain);
unsigned Opc = QOpcodes0[OpcodeIndex];
SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
MVT::Other, Ops.data(), NumVecs+5);
MVT::Other, Ops.data(), NumVecs+7);
Chain = SDValue(VStA, 1);
// Store the odd subregs.
@ -1188,10 +1202,12 @@ SDNode *ARMDAGToDAGISel::SelectVST(SDValue Op, unsigned NumVecs,
for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
Ops[Vec+4] = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
N->getOperand(Vec+3));
Ops[NumVecs+4] = Chain;
Ops[NumVecs+4] = Pred;
Ops[NumVecs+5] = PredReg;
Ops[NumVecs+6] = Chain;
Opc = QOpcodes1[OpcodeIndex];
SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
MVT::Other, Ops.data(), NumVecs+5);
MVT::Other, Ops.data(), NumVecs+7);
Chain = SDValue(VStB, 1);
ReplaceUses(SDValue(N, 0), Chain);
return NULL;
@ -1239,6 +1255,9 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDValue Op, bool IsLoad,
case MVT::v4i32: OpcodeIndex = 1; break;
}
SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SmallVector<SDValue, 9> Ops;
Ops.push_back(MemAddr);
Ops.push_back(MemUpdate);
@ -1264,15 +1283,17 @@ SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDValue Op, bool IsLoad,
N->getOperand(Vec+3)));
}
Ops.push_back(getI32Imm(Lane));
Ops.push_back(Pred);
Ops.push_back(PredReg);
Ops.push_back(Chain);
if (!IsLoad)
return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+5);
return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+7);
std::vector<EVT> ResTys(NumVecs, RegVT);
ResTys.push_back(MVT::Other);
SDNode *VLdLn =
CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), NumVecs+5);
CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), NumVecs+7);
// For a 64-bit vector load to D registers, nothing more needs to be done.
if (is64BitVector)
return VLdLn;
@ -1297,7 +1318,7 @@ SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDValue Op,
return NULL;
unsigned Shl_imm = 0;
if (isOpcWithIntImmediate(Op.getOperand(0).getNode(), ISD::SHL, Shl_imm)){
if (isOpcWithIntImmediate(Op.getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
unsigned Srl_imm = 0;
if (isInt32Immediate(Op.getOperand(1), Srl_imm)) {
@ -1519,7 +1540,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
SDNode *ResNode;
if (Subtarget->isThumb1Only()) {
SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32);
SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
@ -1775,8 +1796,10 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
case MVT::v4f32:
case MVT::v4i32: Opc = ARM::VZIPq32; break;
}
return CurDAG->getMachineNode(Opc, dl, VT, VT,
N->getOperand(0), N->getOperand(1));
SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
}
case ARMISD::VUZP: {
unsigned Opc = 0;
@ -1792,8 +1815,10 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
case MVT::v4f32:
case MVT::v4i32: Opc = ARM::VUZPq32; break;
}
return CurDAG->getMachineNode(Opc, dl, VT, VT,
N->getOperand(0), N->getOperand(1));
SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
}
case ARMISD::VTRN: {
unsigned Opc = 0;
@ -1809,8 +1834,10 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
case MVT::v4f32:
case MVT::v4i32: Opc = ARM::VTRNq32; break;
}
return CurDAG->getMachineNode(Opc, dl, VT, VT,
N->getOperand(0), N->getOperand(1));
SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
}
case ISD::INTRINSIC_VOID:

54
lib/Target/ARM/ARMInstrFormats.td
View File

@ -1217,27 +1217,30 @@ class AVConv5I<bits<8> opcod1, bits<4> opcod2, dag oops, dag iops,
//
class NeonI<dag oops, dag iops, AddrMode am, IndexMode im, InstrItinClass itin,
string asm, string cstr, list<dag> pattern>
string opc, string asm, string cstr, list<dag> pattern>
: InstARM<am, Size4Bytes, im, NEONFrm, NeonDomain, cstr, itin> {
let OutOperandList = oops;
let InOperandList = iops;
let AsmString = asm;
let InOperandList = !con(iops, (ops pred:$p));
let AsmString = !strconcat(opc, !strconcat("${p}", asm));
let Pattern = pattern;
list<Predicate> Predicates = [HasNEON];
}
class NI<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
: NeonI<oops, iops, AddrModeNone, IndexModeNone, itin, asm, "", pattern> {
class NI<dag oops, dag iops, InstrItinClass itin, string opc, string asm,
list<dag> pattern>
: NeonI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm, "",
pattern> {
}
class NI4<dag oops, dag iops, InstrItinClass itin, string asm, list<dag> pattern>
: NeonI<oops, iops, AddrMode4, IndexModeNone, itin, asm, "", pattern> {
class NI4<dag oops, dag iops, InstrItinClass itin, string opc, string asm,
list<dag> pattern>
: NeonI<oops, iops, AddrMode4, IndexModeNone, itin, opc, asm, "", pattern> {
}
class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
dag oops, dag iops, InstrItinClass itin,
string asm, string cstr, list<dag> pattern>
: NeonI<oops, iops, AddrMode6, IndexModeNone, itin, asm, cstr, pattern> {
string opc, string asm, string cstr, list<dag> pattern>
: NeonI<oops, iops, AddrMode6, IndexModeNone, itin, opc, asm, cstr, pattern> {
let Inst{31-24} = 0b11110100;
let Inst{23} = op23;
let Inst{21-20} = op21_20;
@ -1248,8 +1251,8 @@ class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4,
// With selective bit(s) from op7_4 specified by subclasses.
class NLdStLN<bit op23, bits<2> op21_20, bits<4> op11_8,
dag oops, dag iops, InstrItinClass itin,
string asm, string cstr, list<dag> pattern>
: NeonI<oops, iops, AddrMode6, IndexModeNone, itin, asm, cstr, pattern> {
string opc, string asm, string cstr, list<dag> pattern>
: NeonI<oops, iops, AddrMode6, IndexModeNone, itin, opc, asm, cstr, pattern> {
let Inst{31-24} = 0b11110100;
let Inst{23} = op23;
let Inst{21-20} = op21_20;
@ -1257,8 +1260,9 @@ class NLdStLN<bit op23, bits<2> op21_20, bits<4> op11_8,
}
class NDataI<dag oops, dag iops, InstrItinClass itin,
string asm, string cstr, list<dag> pattern>
: NeonI<oops, iops, AddrModeNone, IndexModeNone, itin, asm, cstr, pattern> {
string opc, string asm, string cstr, list<dag> pattern>
: NeonI<oops, iops, AddrModeNone, IndexModeNone, itin, opc, asm,
cstr, pattern> {
let Inst{31-25} = 0b1111001;
}
@ -1266,8 +1270,8 @@ class NDataI<dag oops, dag iops, InstrItinClass itin,
class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
bit op5, bit op4,
dag oops, dag iops, InstrItinClass itin,
string asm, string cstr, list<dag> pattern>
: NDataI<oops, iops, itin, asm, cstr, pattern> {
string opc, string asm, string cstr, list<dag> pattern>
: NDataI<oops, iops, itin, opc, asm, cstr, pattern> {
let Inst{23} = op23;
let Inst{21-19} = op21_19;
let Inst{11-8} = op11_8;
@ -1281,8 +1285,8 @@ class N1ModImm<bit op23, bits<3> op21_19, bits<4> op11_8, bit op7, bit op6,
class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
bits<5> op11_7, bit op6, bit op4,
dag oops, dag iops, InstrItinClass itin,
string asm, string cstr, list<dag> pattern>
: NDataI<oops, iops, itin, asm, cstr, pattern> {
string opc, string asm, string cstr, list<dag> pattern>
: NDataI<oops, iops, itin, opc, asm, cstr, pattern> {
let Inst{24-23} = op24_23;
let Inst{21-20} = op21_20;
let Inst{19-18} = op19_18;
@ -1296,8 +1300,8 @@ class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
// Inst{19-16} is specified by subclasses.
class N2VDup<bits<2> op24_23, bits<2> op21_20, bits<5> op11_7, bit op6, bit op4,
dag oops, dag iops, InstrItinClass itin,
string asm, string cstr, list<dag> pattern>
: NDataI<oops, iops, itin, asm, cstr, pattern> {
string opc, string asm, string cstr, list<dag> pattern>
: NDataI<oops, iops, itin, opc, asm, cstr, pattern> {
let Inst{24-23} = op24_23;
let Inst{21-20} = op21_20;
let Inst{11-7} = op11_7;
@ -1308,8 +1312,8 @@ class N2VDup<bits<2> op24_23, bits<2> op21_20, bits<5> op11_7, bit op6, bit op4,
// NEON 2 vector register with immediate.
class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
dag oops, dag iops, InstrItinClass itin,
string asm, string cstr, list<dag> pattern>
: NDataI<oops, iops, itin, asm, cstr, pattern> {
string opc, string asm, string cstr, list<dag> pattern>
: NDataI<oops, iops, itin, opc, asm, cstr, pattern> {
let Inst{24} = op24;
let Inst{23} = op23;
let Inst{11-8} = op11_8;
@ -1321,8 +1325,8 @@ class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
// NEON 3 vector register format.
class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
dag oops, dag iops, InstrItinClass itin,
string asm, string cstr, list<dag> pattern>
: NDataI<oops, iops, itin, asm, cstr, pattern> {
string opc, string asm, string cstr, list<dag> pattern>
: NDataI<oops, iops, itin, opc, asm, cstr, pattern> {
let Inst{24} = op24;
let Inst{23} = op23;
let Inst{21-20} = op21_20;
@ -1336,8 +1340,8 @@ class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
// concatenation of the operands and is left unspecified.
class N3VImm<bit op24, bit op23, bits<2> op21_20, bit op6, bit op4,
dag oops, dag iops, InstrItinClass itin,
string asm, string cstr, list<dag> pattern>
: NDataI<oops, iops, itin, asm, cstr, pattern> {
string opc, string asm, string cstr, list<dag> pattern>
: NDataI<oops, iops, itin, opc, asm, cstr, pattern> {
let Inst{24} = op24;
let Inst{23} = op23;
let Inst{21-20} = op21_20;

531
lib/Target/ARM/ARMInstrNEON.td
View File

File diff suppressed because it is too large Load Diff

4
lib/Target/ARM/NEONMoveFix.cpp
View File

@ -81,8 +81,8 @@ bool NEONMoveFixPass::InsertMoves(MachineBasicBlock &MBB) {
// afterwards
// - The imp-defs / imp-uses are superregs only, we don't care about
// them.
BuildMI(MBB, *MI, MI->getDebugLoc(),
TII->get(ARM::VMOVDneon), DestReg).addReg(SrcReg);
AddDefaultPred(BuildMI(MBB, *MI, MI->getDebugLoc(),
TII->get(ARM::VMOVDneon), DestReg).addReg(SrcReg));
MBB.erase(MI);
MachineBasicBlock::iterator I = prior(NextMII);
MI = &*I;