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https://github.com/c64scene-ar/llvm-6502.git
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Post process 'xor', 'or' and 'cmp' instructions and select better encoding, if available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148485 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1217,6 +1217,120 @@ processInstruction(MCInst &Inst,
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Inst = TmpInst;
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return true;
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}
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case X86::XOR16i16: {
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if (!Inst.getOperand(0).isImm() ||
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!isImmSExti16i8Value(Inst.getOperand(0).getImm()))
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return false;
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MCInst TmpInst;
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TmpInst.setOpcode(X86::XOR16ri8);
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TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
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TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
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TmpInst.addOperand(Inst.getOperand(0));
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Inst = TmpInst;
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return true;
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}
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case X86::XOR32i32: {
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if (!Inst.getOperand(0).isImm() ||
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!isImmSExti32i8Value(Inst.getOperand(0).getImm()))
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return false;
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MCInst TmpInst;
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TmpInst.setOpcode(X86::XOR32ri8);
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TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
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TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
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TmpInst.addOperand(Inst.getOperand(0));
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Inst = TmpInst;
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return true;
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}
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case X86::XOR64i32: {
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if (!Inst.getOperand(0).isImm() ||
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!isImmSExti64i8Value(Inst.getOperand(0).getImm()))
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return false;
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MCInst TmpInst;
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TmpInst.setOpcode(X86::XOR64ri8);
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TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
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TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
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TmpInst.addOperand(Inst.getOperand(0));
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Inst = TmpInst;
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return true;
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}
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case X86::OR16i16: {
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if (!Inst.getOperand(0).isImm() ||
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!isImmSExti16i8Value(Inst.getOperand(0).getImm()))
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return false;
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MCInst TmpInst;
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TmpInst.setOpcode(X86::OR16ri8);
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TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
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TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
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TmpInst.addOperand(Inst.getOperand(0));
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Inst = TmpInst;
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return true;
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}
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case X86::OR32i32: {
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if (!Inst.getOperand(0).isImm() ||
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!isImmSExti32i8Value(Inst.getOperand(0).getImm()))
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return false;
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MCInst TmpInst;
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TmpInst.setOpcode(X86::OR32ri8);
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TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
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TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
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TmpInst.addOperand(Inst.getOperand(0));
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Inst = TmpInst;
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return true;
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}
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case X86::OR64i32: {
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if (!Inst.getOperand(0).isImm() ||
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!isImmSExti64i8Value(Inst.getOperand(0).getImm()))
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return false;
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MCInst TmpInst;
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TmpInst.setOpcode(X86::OR64ri8);
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TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
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TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
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TmpInst.addOperand(Inst.getOperand(0));
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Inst = TmpInst;
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return true;
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}
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case X86::CMP16i16: {
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if (!Inst.getOperand(0).isImm() ||
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!isImmSExti16i8Value(Inst.getOperand(0).getImm()))
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return false;
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MCInst TmpInst;
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TmpInst.setOpcode(X86::CMP16ri8);
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TmpInst.addOperand(MCOperand::CreateReg(X86::AX));
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TmpInst.addOperand(Inst.getOperand(0));
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Inst = TmpInst;
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return true;
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}
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case X86::CMP32i32: {
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if (!Inst.getOperand(0).isImm() ||
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!isImmSExti32i8Value(Inst.getOperand(0).getImm()))
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return false;
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MCInst TmpInst;
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TmpInst.setOpcode(X86::CMP32ri8);
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TmpInst.addOperand(MCOperand::CreateReg(X86::EAX));
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TmpInst.addOperand(Inst.getOperand(0));
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Inst = TmpInst;
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return true;
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}
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case X86::CMP64i32: {
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if (!Inst.getOperand(0).isImm() ||
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!isImmSExti64i8Value(Inst.getOperand(0).getImm()))
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return false;
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MCInst TmpInst;
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TmpInst.setOpcode(X86::CMP64ri8);
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TmpInst.addOperand(MCOperand::CreateReg(X86::RAX));
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TmpInst.addOperand(Inst.getOperand(0));
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Inst = TmpInst;
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return true;
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}
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}
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return false;
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}
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22
test/MC/X86/intel-syntax-encoding.s
Normal file
22
test/MC/X86/intel-syntax-encoding.s
Normal file
@ -0,0 +1,22 @@
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// RUN: llvm-mc -x86-asm-syntax=intel -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
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// CHECK: encoding: [0x66,0x83,0xf0,0x0c]
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xor ax, 12
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// CHECK: encoding: [0x83,0xf0,0x0c]
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xor eax, 12
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// CHECK: encoding: [0x48,0x83,0xf0,0x0c]
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xor rax, 12
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// CHECK: encoding: [0x66,0x83,0xc8,0x0c]
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or ax, 12
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// CHECK: encoding: [0x83,0xc8,0x0c]
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or eax, 12
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// CHECK: encoding: [0x48,0x83,0xc8,0x0c]
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or rax, 12
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// CHECK: encoding: [0x66,0x83,0xf8,0x0c]
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cmp ax, 12
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// CHECK: encoding: [0x83,0xf8,0x0c]
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cmp eax, 12
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// CHECK: encoding: [0x48,0x83,0xf8,0x0c]
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cmp rax, 12
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