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https://github.com/c64scene-ar/llvm-6502.git
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Replace copyRegToReg with copyPhysReg for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108078 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -120,34 +120,26 @@ isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
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NumT <= (IfCvtDiamondLimit) && NumF <= (IfCvtDiamondLimit);
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}
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bool
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Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC,
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DebugLoc DL) const {
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if (DestRC == ARM::GPRRegisterClass || DestRC == ARM::tcGPRRegisterClass) {
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if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) {
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BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
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return true;
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} else if (SrcRC == ARM::tGPRRegisterClass) {
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BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
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return true;
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}
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} else if (DestRC == ARM::tGPRRegisterClass) {
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if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) {
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BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
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return true;
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} else if (SrcRC == ARM::tGPRRegisterClass) {
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BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
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return true;
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}
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}
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void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const {
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// Handle SPR, DPR, and QPR copies.
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return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC,
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SrcRC, DL);
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if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
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return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
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bool tDest = ARM::tGPRRegClass.contains(DestReg);
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bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
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unsigned Opc = ARM::tMOVgpr2gpr;
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if (tDest && tSrc)
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Opc = ARM::tMOVr;
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else if (tSrc)
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Opc = ARM::tMOVtgpr2gpr;
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else if (tDest)
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Opc = ARM::tMOVgpr2tgpr;
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BuildMI(MBB, I, DL, get(Opc), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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}
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void Thumb2InstrInfo::
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