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Add <imp-def> operands to QQ and QQQQ stack loads.

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This pleases the register scavenger and brings
test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll a little closer to
working with -verify-machineinstrs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138164 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-08-20 00:17:45 +00:00
parent e5038e191d
commit ac3656ed7a
1 changed files with 4 additions and 2 deletions
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6
lib/Target/ARM/ARMBaseInstrInfo.cpp
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@ -930,7 +930,8 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI);
AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::Define, TRI);
MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
}
} else
llvm_unreachable("Unknown reg class!");
@ -948,7 +949,8 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::Define, TRI);
AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::Define, TRI);
MIB.addReg(DestReg, RegState::Define | RegState::Implicit);
} else
llvm_unreachable("Unknown reg class!");
break;