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Track IR ordering of SelectionDAG nodes 2/4.

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Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
2013-05-25 02:42:55 +00:00
parent ea5db0c315
commit ac6d9bec67
74 changed files with 2187 additions and 2190 deletions
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20
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
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@ -320,7 +320,7 @@ SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
assert(Op.getNode()->getNumValues() == 1 &&
"Can't promote a vector with multiple results!");
MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
DebugLoc dl = Op.getDebugLoc();
SDLoc dl(Op);;
SmallVector<SDValue, 4> Operands(Op.getNumOperands());
for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
@ -357,7 +357,7 @@ SDValue VectorLegalizer::PromoteVectorOpINT_TO_FP(SDValue Op) {
// Build a new vector type and check if it is legal.
MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
DebugLoc dl = Op.getDebugLoc();
SDLoc dl(Op);;
SmallVector<SDValue, 4> Operands(Op.getNumOperands());
unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
@ -375,7 +375,7 @@ SDValue VectorLegalizer::PromoteVectorOpINT_TO_FP(SDValue Op) {
SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
DebugLoc dl = Op.getDebugLoc();
SDLoc dl(Op);;
LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
SDValue Chain = LD->getChain();
SDValue BasePTR = LD->getBasePtr();
@ -519,7 +519,7 @@ SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
}
SDValue VectorLegalizer::ExpandStore(SDValue Op) {
DebugLoc dl = Op.getDebugLoc();
SDLoc dl(Op);;
StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
SDValue Chain = ST->getChain();
SDValue BasePTR = ST->getBasePtr();
@ -574,7 +574,7 @@ SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
// operands are vectors. Lower this select to VSELECT and implement it
// using XOR AND OR. The selector bit is broadcasted.
EVT VT = Op.getValueType();
DebugLoc DL = Op.getDebugLoc();
SDLoc DL(Op);;
SDValue Mask = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
@ -637,7 +637,7 @@ SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
return DAG.UnrollVectorOp(Op.getNode());
DebugLoc DL = Op.getDebugLoc();
SDLoc DL(Op);;
EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
unsigned BW = VT.getScalarType().getSizeInBits();
@ -652,7 +652,7 @@ SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
// Implement VSELECT in terms of XOR, AND, OR
// on platforms which do not support blend natively.
DebugLoc DL = Op.getDebugLoc();
SDLoc DL(Op);;
SDValue Mask = Op.getOperand(0);
SDValue Op1 = Op.getOperand(1);
@ -698,7 +698,7 @@ SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
EVT VT = Op.getOperand(0).getValueType();
DebugLoc DL = Op.getDebugLoc();
SDLoc DL(Op);;
// Make sure that the SINT_TO_FP and SRL instructions are available.
if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
@ -739,7 +739,7 @@ SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
SDValue Zero = DAG.getConstantFP(-0.0, Op.getValueType());
return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
Zero, Op.getOperand(0));
}
return DAG.UnrollVectorOp(Op.getNode());
@ -751,7 +751,7 @@ SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
EVT EltVT = VT.getVectorElementType();
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
EVT TmpEltVT = LHS.getValueType().getVectorElementType();
DebugLoc dl = Op.getDebugLoc();
SDLoc dl(Op);;
SmallVector<SDValue, 8> Ops(NumElems);
for (unsigned i = 0; i < NumElems; ++i) {
SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,