mirror of
https://github.com/c64scene-ar/llvm-6502.git
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[bpf] add big- and host- endian support
Summary: -march=bpf -> host endian -march=bpf_le -> little endian -match=bpf_be -> big endian Test Plan: v1 was tested by IBM s390 guys and appears to be working there. It bit rots too fast here. Reviewers: chandlerc, tstellarAMD Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10177 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239071 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -50,7 +50,8 @@ public:
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armeb, // ARM (big endian): armeb
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aarch64, // AArch64 (little endian): aarch64
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aarch64_be, // AArch64 (big endian): aarch64_be
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bpf, // eBPF or extended BPF or 64-bit BPF (little endian)
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bpf_le, // eBPF or extended BPF or 64-bit BPF (little endian)
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bpf_be, // eBPF or extended BPF or 64-bit BPF (big endian)
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hexagon, // Hexagon: hexagon
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mips, // MIPS: mips, mipsallegrex
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mipsel, // MIPSEL: mipsel, mipsallegrexel
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@ -13,6 +13,7 @@
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetParser.h"
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#include "llvm/Support/Host.h"
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#include <cstring>
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using namespace llvm;
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@ -24,7 +25,8 @@ const char *Triple::getArchTypeName(ArchType Kind) {
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case aarch64_be: return "aarch64_be";
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case arm: return "arm";
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case armeb: return "armeb";
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case bpf: return "bpf";
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case bpf_le: return "bpf_le";
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case bpf_be: return "bpf_be";
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case hexagon: return "hexagon";
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case mips: return "mips";
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case mipsel: return "mipsel";
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@ -89,7 +91,8 @@ const char *Triple::getArchTypePrefix(ArchType Kind) {
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case amdgcn:
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case r600: return "amdgpu";
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case bpf: return "bpf";
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case bpf_le:
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case bpf_be: return "bpf";
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case sparcv9:
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case sparcel:
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@ -192,14 +195,30 @@ const char *Triple::getEnvironmentTypeName(EnvironmentType Kind) {
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llvm_unreachable("Invalid EnvironmentType!");
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}
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static Triple::ArchType parseBPFArch(StringRef ArchName) {
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if (ArchName.equals("bpf")) {
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if (sys::IsLittleEndianHost)
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return Triple::bpf_le;
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else
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return Triple::bpf_be;
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} else if (ArchName.equals("bpf_be")) {
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return Triple::bpf_be;
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} else if (ArchName.equals("bpf_le")) {
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return Triple::bpf_le;
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} else {
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return Triple::UnknownArch;
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}
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}
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Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
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Triple::ArchType BPFArch(parseBPFArch(Name));
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return StringSwitch<Triple::ArchType>(Name)
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.Case("aarch64", aarch64)
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.Case("aarch64_be", aarch64_be)
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.Case("arm64", aarch64) // "arm64" is an alias for "aarch64"
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.Case("arm", arm)
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.Case("armeb", armeb)
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.Case("bpf", bpf)
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.StartsWith("bpf", BPFArch)
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.Case("mips", mips)
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.Case("mipsel", mipsel)
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.Case("mips64", mips64)
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@ -296,6 +315,7 @@ static Triple::ArchType parseARMArch(StringRef ArchName) {
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static Triple::ArchType parseArch(StringRef ArchName) {
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Triple::ArchType ARMArch(parseARMArch(ArchName));
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Triple::ArchType BPFArch(parseBPFArch(ArchName));
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return StringSwitch<Triple::ArchType>(ArchName)
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.Cases("i386", "i486", "i586", "i686", Triple::x86)
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@ -317,7 +337,7 @@ static Triple::ArchType parseArch(StringRef ArchName) {
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.Case("mips64el", Triple::mips64el)
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.Case("r600", Triple::r600)
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.Case("amdgcn", Triple::amdgcn)
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.Case("bpf", Triple::bpf)
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.StartsWith("bpf", BPFArch)
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.Case("hexagon", Triple::hexagon)
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.Case("s390x", Triple::systemz)
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.Case("sparc", Triple::sparc)
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@ -989,7 +1009,8 @@ static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
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case llvm::Triple::aarch64:
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case llvm::Triple::aarch64_be:
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case llvm::Triple::amdgcn:
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case llvm::Triple::bpf:
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case llvm::Triple::bpf_le:
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case llvm::Triple::bpf_be:
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case llvm::Triple::le64:
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case llvm::Triple::mips64:
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case llvm::Triple::mips64el:
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@ -1026,7 +1047,8 @@ Triple Triple::get32BitArchVariant() const {
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case Triple::aarch64:
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case Triple::aarch64_be:
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case Triple::amdgcn:
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case Triple::bpf:
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case Triple::bpf_le:
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case Triple::bpf_be:
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case Triple::msp430:
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case Triple::systemz:
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case Triple::ppc64le:
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@ -1090,7 +1112,8 @@ Triple Triple::get64BitArchVariant() const {
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case Triple::aarch64:
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case Triple::aarch64_be:
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case Triple::bpf:
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case Triple::bpf_le:
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case Triple::bpf_be:
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case Triple::le64:
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case Triple::amdil64:
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case Triple::amdgcn:
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@ -83,5 +83,7 @@ void BPFAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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// Force static initialization.
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extern "C" void LLVMInitializeBPFAsmPrinter() {
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RegisterAsmPrinter<BPFAsmPrinter> X(TheBPFTarget);
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RegisterAsmPrinter<BPFAsmPrinter> X(TheBPFleTarget);
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RegisterAsmPrinter<BPFAsmPrinter> Y(TheBPFbeTarget);
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RegisterAsmPrinter<BPFAsmPrinter> Z(TheBPFTarget);
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}
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@ -23,19 +23,24 @@ using namespace llvm;
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extern "C" void LLVMInitializeBPFTarget() {
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// Register the target.
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RegisterTargetMachine<BPFTargetMachine> X(TheBPFTarget);
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RegisterTargetMachine<BPFTargetMachine> X(TheBPFleTarget);
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RegisterTargetMachine<BPFTargetMachine> Y(TheBPFbeTarget);
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RegisterTargetMachine<BPFTargetMachine> Z(TheBPFTarget);
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}
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// DataLayout: little or big endian
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static std::string computeDataLayout(StringRef TT) {
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if (Triple(TT).getArch() == Triple::bpf_be)
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return "E-m:e-p:64:64-i64:64-n32:64-S128";
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else
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return "e-m:e-p:64:64-i64:64-n32:64-S128";
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}
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// DataLayout --> Little-endian, 64-bit pointer/ABI/alignment
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// The stack is always 8 byte aligned
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// On function prologue, the stack is created by decrementing
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// its pointer. Once decremented, all references are done with positive
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// offset from the stack/frame pointer.
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BPFTargetMachine::BPFTargetMachine(const Target &T, StringRef TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, "e-m:e-p:64:64-i64:64-n32:64-S128", TT, CPU, FS,
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: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS,
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Options, RM, CM, OL),
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TLOF(make_unique<TargetLoweringObjectFileELF>()),
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Subtarget(TT, CPU, FS, *this) {
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@ -25,7 +25,10 @@ using namespace llvm;
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namespace {
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class BPFAsmBackend : public MCAsmBackend {
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public:
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BPFAsmBackend() : MCAsmBackend() {}
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bool IsLittleEndian;
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BPFAsmBackend(bool IsLittleEndian)
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: MCAsmBackend(), IsLittleEndian(IsLittleEndian) {}
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~BPFAsmBackend() override {}
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void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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@ -69,17 +72,28 @@ void BPFAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
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}
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assert(Fixup.getKind() == FK_PCRel_2);
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Value = (uint16_t)((Value - 8) / 8);
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Data[Fixup.getOffset() + 2] = Value & 0xFF;
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Data[Fixup.getOffset() + 3] = Value >> 8;
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if (IsLittleEndian) {
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Data[Fixup.getOffset() + 2] = Value & 0xFF;
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Data[Fixup.getOffset() + 3] = Value >> 8;
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} else {
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Data[Fixup.getOffset() + 2] = Value >> 8;
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Data[Fixup.getOffset() + 3] = Value & 0xFF;
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}
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}
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MCObjectWriter *BPFAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
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return createBPFELFObjectWriter(OS, 0);
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return createBPFELFObjectWriter(OS, 0, IsLittleEndian);
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}
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}
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MCAsmBackend *llvm::createBPFAsmBackend(const Target &T,
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const MCRegisterInfo &MRI, StringRef TT,
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StringRef CPU) {
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return new BPFAsmBackend();
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return new BPFAsmBackend(/*IsLittleEndian=*/true);
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}
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MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T,
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const MCRegisterInfo &MRI, StringRef TT,
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StringRef CPU) {
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return new BPFAsmBackend(/*IsLittleEndian=*/false);
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}
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@ -47,7 +47,8 @@ unsigned BPFELFObjectWriter::GetRelocType(const MCValue &Target,
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}
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}
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MCObjectWriter *llvm::createBPFELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI) {
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MCObjectWriter *llvm::createBPFELFObjectWriter(raw_pwrite_stream &OS,
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uint8_t OSABI, bool IsLittleEndian) {
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MCELFObjectTargetWriter *MOTW = new BPFELFObjectWriter(OSABI);
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return createELFObjectWriter(MOTW, OS, /*IsLittleEndian=*/true);
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return createELFObjectWriter(MOTW, OS, IsLittleEndian);
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}
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@ -16,6 +16,7 @@
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#include "llvm/ADT/StringRef.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/ADT/Triple.h"
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namespace llvm {
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class Target;
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@ -24,6 +25,9 @@ class Triple;
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class BPFMCAsmInfo : public MCAsmInfo {
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public:
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explicit BPFMCAsmInfo(const Triple &TT) {
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if (TT.getArch() == Triple::bpf_be)
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IsLittleEndian = false;
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PrivateGlobalPrefix = ".L";
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WeakRefDirective = "\t.weak\t";
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@ -30,9 +30,11 @@ class BPFMCCodeEmitter : public MCCodeEmitter {
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BPFMCCodeEmitter(const BPFMCCodeEmitter &) = delete;
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void operator=(const BPFMCCodeEmitter &) = delete;
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const MCRegisterInfo &MRI;
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bool IsLittleEndian;
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public:
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BPFMCCodeEmitter(const MCRegisterInfo &mri) : MRI(mri) {}
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BPFMCCodeEmitter(const MCRegisterInfo &mri, bool IsLittleEndian)
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: MRI(mri), IsLittleEndian(IsLittleEndian) {}
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~BPFMCCodeEmitter() {}
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@ -61,7 +63,13 @@ public:
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MCCodeEmitter *llvm::createBPFMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx) {
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return new BPFMCCodeEmitter(MRI);
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return new BPFMCCodeEmitter(MRI, true);
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}
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MCCodeEmitter *llvm::createBPFbeMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx) {
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return new BPFMCCodeEmitter(MRI, false);
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}
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unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI,
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@ -91,32 +99,53 @@ unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI,
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return 0;
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}
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static uint8_t SwapBits(uint8_t Val)
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{
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return (Val & 0x0F) << 4 | (Val & 0xF0) >> 4;
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}
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void BPFMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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unsigned Opcode = MI.getOpcode();
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support::endian::Writer<support::little> LE(OS);
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support::endian::Writer<support::big> BE(OS);
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if (Opcode == BPF::LD_imm64 || Opcode == BPF::LD_pseudo) {
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uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
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LE.write<uint8_t>(Value >> 56);
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LE.write<uint8_t>(((Value >> 48) & 0xff));
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if (IsLittleEndian)
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LE.write<uint8_t>((Value >> 48) & 0xff);
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else
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LE.write<uint8_t>(SwapBits((Value >> 48) & 0xff));
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LE.write<uint16_t>(0);
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LE.write<uint32_t>(Value & 0xffffFFFF);
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if (IsLittleEndian)
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LE.write<uint32_t>(Value & 0xffffFFFF);
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else
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BE.write<uint32_t>(Value & 0xffffFFFF);
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const MCOperand &MO = MI.getOperand(1);
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uint64_t Imm = MO.isImm() ? MO.getImm() : 0;
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LE.write<uint8_t>(0);
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LE.write<uint8_t>(0);
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LE.write<uint16_t>(0);
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LE.write<uint32_t>(Imm >> 32);
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if (IsLittleEndian)
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LE.write<uint32_t>(Imm >> 32);
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else
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BE.write<uint32_t>(Imm >> 32);
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} else {
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// Get instruction encoding and emit it
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uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
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LE.write<uint8_t>(Value >> 56);
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LE.write<uint8_t>((Value >> 48) & 0xff);
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LE.write<uint16_t>((Value >> 32) & 0xffff);
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LE.write<uint32_t>(Value & 0xffffFFFF);
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if (IsLittleEndian) {
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LE.write<uint8_t>((Value >> 48) & 0xff);
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LE.write<uint16_t>((Value >> 32) & 0xffff);
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LE.write<uint32_t>(Value & 0xffffFFFF);
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} else {
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LE.write<uint8_t>(SwapBits((Value >> 48) & 0xff));
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BE.write<uint16_t>((Value >> 32) & 0xffff);
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BE.write<uint32_t>(Value & 0xffffFFFF);
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}
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}
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}
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@ -79,32 +79,43 @@ static MCInstPrinter *createBPFMCInstPrinter(const Triple &T,
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}
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extern "C" void LLVMInitializeBPFTargetMC() {
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// Register the MC asm info.
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RegisterMCAsmInfo<BPFMCAsmInfo> X(TheBPFTarget);
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for (Target *T : {&TheBPFleTarget, &TheBPFbeTarget, &TheBPFTarget}) {
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// Register the MC asm info.
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RegisterMCAsmInfo<BPFMCAsmInfo> X(*T);
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// Register the MC codegen info.
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TargetRegistry::RegisterMCCodeGenInfo(TheBPFTarget, createBPFMCCodeGenInfo);
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// Register the MC codegen info.
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TargetRegistry::RegisterMCCodeGenInfo(*T, createBPFMCCodeGenInfo);
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// Register the MC instruction info.
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TargetRegistry::RegisterMCInstrInfo(TheBPFTarget, createBPFMCInstrInfo);
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// Register the MC instruction info.
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TargetRegistry::RegisterMCInstrInfo(*T, createBPFMCInstrInfo);
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// Register the MC register info.
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TargetRegistry::RegisterMCRegInfo(TheBPFTarget, createBPFMCRegisterInfo);
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// Register the MC register info.
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TargetRegistry::RegisterMCRegInfo(*T, createBPFMCRegisterInfo);
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// Register the MC subtarget info.
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TargetRegistry::RegisterMCSubtargetInfo(TheBPFTarget,
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createBPFMCSubtargetInfo);
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// Register the MC subtarget info.
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TargetRegistry::RegisterMCSubtargetInfo(*T,
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createBPFMCSubtargetInfo);
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// Register the object streamer
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TargetRegistry::RegisterELFStreamer(*T, createBPFMCStreamer);
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// Register the MCInstPrinter.
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TargetRegistry::RegisterMCInstPrinter(*T, createBPFMCInstPrinter);
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}
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// Register the MC code emitter
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TargetRegistry::RegisterMCCodeEmitter(TheBPFTarget,
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llvm::createBPFMCCodeEmitter);
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TargetRegistry::RegisterMCCodeEmitter(TheBPFleTarget, createBPFMCCodeEmitter);
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TargetRegistry::RegisterMCCodeEmitter(TheBPFbeTarget, createBPFbeMCCodeEmitter);
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// Register the ASM Backend
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TargetRegistry::RegisterMCAsmBackend(TheBPFTarget, createBPFAsmBackend);
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TargetRegistry::RegisterMCAsmBackend(TheBPFleTarget, createBPFAsmBackend);
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TargetRegistry::RegisterMCAsmBackend(TheBPFbeTarget, createBPFbeAsmBackend);
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// Register the object streamer
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TargetRegistry::RegisterELFStreamer(TheBPFTarget, createBPFMCStreamer);
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// Register the MCInstPrinter.
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TargetRegistry::RegisterMCInstPrinter(TheBPFTarget, createBPFMCInstPrinter);
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if (sys::IsLittleEndianHost) {
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TargetRegistry::RegisterMCCodeEmitter(TheBPFTarget, createBPFMCCodeEmitter);
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TargetRegistry::RegisterMCAsmBackend(TheBPFTarget, createBPFAsmBackend);
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} else {
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TargetRegistry::RegisterMCCodeEmitter(TheBPFTarget, createBPFbeMCCodeEmitter);
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TargetRegistry::RegisterMCAsmBackend(TheBPFTarget, createBPFbeAsmBackend);
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}
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}
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@ -30,16 +30,24 @@ class StringRef;
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class raw_ostream;
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class raw_pwrite_stream;
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extern Target TheBPFleTarget;
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extern Target TheBPFbeTarget;
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extern Target TheBPFTarget;
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MCCodeEmitter *createBPFMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx);
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MCCodeEmitter *createBPFbeMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx);
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|
||||
MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI,
|
||||
StringRef TT, StringRef CPU);
|
||||
MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI,
|
||||
StringRef TT, StringRef CPU);
|
||||
|
||||
MCObjectWriter *createBPFELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI);
|
||||
MCObjectWriter *createBPFELFObjectWriter(raw_pwrite_stream &OS,
|
||||
uint8_t OSABI, bool IsLittleEndian);
|
||||
}
|
||||
|
||||
// Defines symbolic names for BPF registers. This defines a mapping from
|
||||
|
@ -11,8 +11,18 @@
|
||||
#include "llvm/Support/TargetRegistry.h"
|
||||
using namespace llvm;
|
||||
|
||||
Target llvm::TheBPFTarget;
|
||||
namespace llvm {
|
||||
Target TheBPFleTarget;
|
||||
Target TheBPFbeTarget;
|
||||
Target TheBPFTarget;
|
||||
}
|
||||
|
||||
extern "C" void LLVMInitializeBPFTargetInfo() {
|
||||
RegisterTarget<Triple::bpf, /*HasJIT=*/true> X(TheBPFTarget, "bpf", "BPF");
|
||||
TargetRegistry::RegisterTarget(TheBPFTarget, "bpf",
|
||||
"BPF (host endian)",
|
||||
[](Triple::ArchType) { return false; }, true);
|
||||
RegisterTarget<Triple::bpf_le, /*HasJIT=*/true> X(
|
||||
TheBPFleTarget, "bpf_le", "BPF (little endian)");
|
||||
RegisterTarget<Triple::bpf_be, /*HasJIT=*/true> Y(
|
||||
TheBPFbeTarget, "bpf_be", "BPF (big endian)");
|
||||
}
|
||||
|
@ -1,5 +1,4 @@
|
||||
; RUN: llc -march=bpf -show-mc-encoding < %s | FileCheck %s
|
||||
; test little endian only for now
|
||||
; RUN: llc -march=bpf_le -show-mc-encoding < %s | FileCheck %s
|
||||
|
||||
define i8 @mov(i8 %a, i8 %b) nounwind {
|
||||
; CHECK-LABEL: mov:
|
||||
|
@ -1,5 +1,4 @@
|
||||
; RUN: llc < %s -march=bpf -verify-machineinstrs -show-mc-encoding | FileCheck %s
|
||||
; test little endian only for now
|
||||
; RUN: llc < %s -march=bpf_le -verify-machineinstrs -show-mc-encoding | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: test_load_add_32
|
||||
; CHECK: xadd32
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -march=bpf | FileCheck %s
|
||||
; RUN: llc < %s -march=bpf_le | FileCheck %s
|
||||
|
||||
define i32 @test0(i32 %X) {
|
||||
%tmp.1 = add i32 %X, 1
|
||||
|
@ -1,5 +1,4 @@
|
||||
; RUN: llc < %s -march=bpf -show-mc-encoding | FileCheck %s
|
||||
; test little endian only for now
|
||||
; RUN: llc < %s -march=bpf_le -show-mc-encoding | FileCheck %s
|
||||
|
||||
define void @test() #0 {
|
||||
entry:
|
||||
|
96
test/CodeGen/BPF/cc_args_be.ll
Normal file
96
test/CodeGen/BPF/cc_args_be.ll
Normal file
@ -0,0 +1,96 @@
|
||||
; RUN: llc < %s -march=bpf_be -show-mc-encoding | FileCheck %s
|
||||
; test big endian
|
||||
|
||||
define void @test() #0 {
|
||||
entry:
|
||||
; CHECK: test:
|
||||
|
||||
; CHECK: mov r1, 123 # encoding: [0xb7,0x10,0x00,0x00,0x00,0x00,0x00,0x7b]
|
||||
; CHECK: call f_i16
|
||||
call void @f_i16(i16 123)
|
||||
|
||||
; CHECK: mov r1, 12345678 # encoding: [0xb7,0x10,0x00,0x00,0x00,0xbc,0x61,0x4e]
|
||||
; CHECK: call f_i32
|
||||
call void @f_i32(i32 12345678)
|
||||
|
||||
; CHECK: ld_64 r1, 72623859790382856 # encoding: [0x18,0x10,0x00,0x00,0x05,0x06,0x07,0x08,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04]
|
||||
; CHECK: call f_i64
|
||||
call void @f_i64(i64 72623859790382856)
|
||||
|
||||
; CHECK: mov r1, 1234
|
||||
; CHECK: mov r2, 5678
|
||||
; CHECK: call f_i32_i32
|
||||
call void @f_i32_i32(i32 1234, i32 5678)
|
||||
|
||||
; CHECK: mov r1, 2
|
||||
; CHECK: mov r2, 3
|
||||
; CHECK: mov r3, 4
|
||||
; CHECK: call f_i16_i32_i16
|
||||
call void @f_i16_i32_i16(i16 2, i32 3, i16 4)
|
||||
|
||||
; CHECK: mov r1, 5
|
||||
; CHECK: ld_64 r2, 7262385979038285
|
||||
; CHECK: mov r3, 6
|
||||
; CHECK: call f_i16_i64_i16
|
||||
call void @f_i16_i64_i16(i16 5, i64 7262385979038285, i16 6)
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
@g_i16 = common global i16 0, align 2
|
||||
@g_i32 = common global i32 0, align 2
|
||||
@g_i64 = common global i64 0, align 4
|
||||
|
||||
define void @f_i16(i16 %a) #0 {
|
||||
; CHECK: f_i16:
|
||||
; CHECK: sth 0(r2), r1 # encoding: [0x6b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
|
||||
store volatile i16 %a, i16* @g_i16, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @f_i32(i32 %a) #0 {
|
||||
; CHECK: f_i32:
|
||||
; CHECK: sth 2(r2), r1 # encoding: [0x6b,0x21,0x00,0x02,0x00,0x00,0x00,0x00]
|
||||
; CHECK: sth 0(r2), r1 # encoding: [0x6b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]
|
||||
store volatile i32 %a, i32* @g_i32, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @f_i64(i64 %a) #0 {
|
||||
; CHECK: f_i64:
|
||||
; CHECK: stw 4(r2), r1 # encoding: [0x63,0x21,0x00,0x04,0x00,0x00,0x00,0x00]
|
||||
; CHECK: stw 0(r2), r1
|
||||
store volatile i64 %a, i64* @g_i64, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @f_i32_i32(i32 %a, i32 %b) #0 {
|
||||
; CHECK: f_i32_i32:
|
||||
; CHECK: stw 0(r3), r1
|
||||
store volatile i32 %a, i32* @g_i32, align 4
|
||||
; CHECK: stw 0(r3), r2
|
||||
store volatile i32 %b, i32* @g_i32, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @f_i16_i32_i16(i16 %a, i32 %b, i16 %c) #0 {
|
||||
; CHECK: f_i16_i32_i16:
|
||||
; CHECK: sth 0(r4), r1
|
||||
store volatile i16 %a, i16* @g_i16, align 2
|
||||
; CHECK: stw 0(r1), r2
|
||||
store volatile i32 %b, i32* @g_i32, align 4
|
||||
; CHECK: sth 0(r4), r3
|
||||
store volatile i16 %c, i16* @g_i16, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @f_i16_i64_i16(i16 %a, i64 %b, i16 %c) #0 {
|
||||
; CHECK: f_i16_i64_i16:
|
||||
; CHECK: sth 0(r4), r1
|
||||
store volatile i16 %a, i16* @g_i16, align 2
|
||||
; CHECK: std 0(r1), r2 # encoding: [0x7b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]
|
||||
store volatile i64 %b, i64* @g_i64, align 8
|
||||
; CHECK: sth 0(r4), r3
|
||||
store volatile i16 %c, i16* @g_i16, align 2
|
||||
ret void
|
||||
}
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -march=bpf | FileCheck %s
|
||||
; RUN: llc < %s -march=bpf_le | FileCheck %s
|
||||
|
||||
define void @test() #0 {
|
||||
entry:
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -march=bpf | FileCheck %s
|
||||
; RUN: llc < %s -march=bpf_le | FileCheck %s
|
||||
|
||||
%struct.bpf_context = type { i64, i64, i64, i64, i64, i64, i64 }
|
||||
%struct.sk_buff = type { i64, i64, i64, i64, i64, i64, i64 }
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -march=bpf -show-mc-encoding | FileCheck %s
|
||||
; RUN: llc < %s -march=bpf_le -show-mc-encoding | FileCheck %s
|
||||
|
||||
; Function Attrs: nounwind uwtable
|
||||
define i32 @ld_b(i64 %foo, i64* nocapture %bar, i8* %ctx, i8* %ctx2) #0 {
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -march=bpf | FileCheck %s
|
||||
; RUN: llc < %s -march=bpf_le | FileCheck %s
|
||||
|
||||
define i16 @am1(i16* %a) nounwind {
|
||||
%1 = load i16, i16* %a
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -march=bpf | FileCheck %s
|
||||
; RUN: llc < %s -march=bpf_le | FileCheck %s
|
||||
|
||||
define zeroext i16 @add(i16* nocapture %a, i16 zeroext %n) nounwind readonly {
|
||||
entry:
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -march=bpf | FileCheck %s
|
||||
; RUN: llc < %s -march=bpf_le | FileCheck %s
|
||||
|
||||
@foo_printf.fmt = private unnamed_addr constant [9 x i8] c"hello \0A\00", align 1
|
||||
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc -march=bpf < %s | FileCheck %s
|
||||
; RUN: llc -march=bpf_le < %s | FileCheck %s
|
||||
|
||||
define i16 @sccweqand(i16 %a, i16 %b) nounwind {
|
||||
%t1 = and i16 %a, %b
|
||||
|
@ -1,5 +1,4 @@
|
||||
; RUN: llc < %s -march=bpf -show-mc-encoding | FileCheck %s
|
||||
; test little endian only for now
|
||||
; RUN: llc < %s -march=bpf_le -show-mc-encoding | FileCheck %s
|
||||
|
||||
define zeroext i8 @lshr8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone {
|
||||
entry:
|
||||
|
@ -1,5 +1,4 @@
|
||||
; RUN: llc < %s -march=bpf -show-mc-encoding | FileCheck %s
|
||||
; test little endian only for now
|
||||
; RUN: llc < %s -march=bpf_le -show-mc-encoding | FileCheck %s
|
||||
|
||||
%struct.bpf_map_def = type { i32, i32, i32, i32 }
|
||||
%struct.sk_buff = type opaque
|
||||
|
Loading…
Reference in New Issue
Block a user