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Simplify classes for shift instructions, which are never commutable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117398 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1291,12 +1291,12 @@ class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
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}
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class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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Format f, InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
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ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
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: N3V<op24, op23, op21_20, op11_8, 0, op4,
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(outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
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OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
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[(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
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let isCommutable = Commutable;
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let isCommutable = 0;
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}
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class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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@ -1334,12 +1334,12 @@ class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
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}
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class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
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Format f, InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
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ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
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: N3V<op24, op23, op21_20, op11_8, 1, op4,
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(outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
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OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
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[(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
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let isCommutable = Commutable;
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let isCommutable = 0;
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}
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// Multiply-Add/Sub operations: single-, double- and quad-register.
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@ -1958,22 +1958,22 @@ multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
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InstrItinClass itinD16, InstrItinClass itinD32,
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InstrItinClass itinQ16, InstrItinClass itinQ32,
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string OpcodeStr, string Dt,
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Intrinsic IntOp, bit Commutable = 0> {
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Intrinsic IntOp> {
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// 64-bit vector types.
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def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
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OpcodeStr, !strconcat(Dt, "16"),
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v4i16, v4i16, IntOp, Commutable>;
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v4i16, v4i16, IntOp>;
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def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
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OpcodeStr, !strconcat(Dt, "32"),
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v2i32, v2i32, IntOp, Commutable>;
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v2i32, v2i32, IntOp>;
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// 128-bit vector types.
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def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
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OpcodeStr, !strconcat(Dt, "16"),
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v8i16, v8i16, IntOp, Commutable>;
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v8i16, v8i16, IntOp>;
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def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
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OpcodeStr, !strconcat(Dt, "32"),
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v4i32, v4i32, IntOp, Commutable>;
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v4i32, v4i32, IntOp>;
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}
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multiclass N3VIntSL_HS<bits<4> op11_8,
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@ -2009,15 +2009,15 @@ multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
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InstrItinClass itinD16, InstrItinClass itinD32,
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InstrItinClass itinQ16, InstrItinClass itinQ32,
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string OpcodeStr, string Dt,
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Intrinsic IntOp, bit Commutable = 0>
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Intrinsic IntOp>
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: N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
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OpcodeStr, Dt, IntOp, Commutable> {
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OpcodeStr, Dt, IntOp> {
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def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
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OpcodeStr, !strconcat(Dt, "8"),
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v8i8, v8i8, IntOp, Commutable>;
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v8i8, v8i8, IntOp>;
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def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
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OpcodeStr, !strconcat(Dt, "8"),
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v16i8, v16i8, IntOp, Commutable>;
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v16i8, v16i8, IntOp>;
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}
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@ -2040,15 +2040,15 @@ multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
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InstrItinClass itinD16, InstrItinClass itinD32,
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InstrItinClass itinQ16, InstrItinClass itinQ32,
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string OpcodeStr, string Dt,
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Intrinsic IntOp, bit Commutable = 0>
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Intrinsic IntOp>
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: N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
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OpcodeStr, Dt, IntOp, Commutable> {
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OpcodeStr, Dt, IntOp> {
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def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
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OpcodeStr, !strconcat(Dt, "64"),
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v1i64, v1i64, IntOp, Commutable>;
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v1i64, v1i64, IntOp>;
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def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
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OpcodeStr, !strconcat(Dt, "64"),
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v2i64, v2i64, IntOp, Commutable>;
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v2i64, v2i64, IntOp>;
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}
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// Neon Narrowing 3-register vector intrinsics,
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@ -3230,10 +3230,10 @@ def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
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// VSHL : Vector Shift
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defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
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IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
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"vshl", "s", int_arm_neon_vshifts, 0>;
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"vshl", "s", int_arm_neon_vshifts>;
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defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
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IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
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"vshl", "u", int_arm_neon_vshiftu, 0>;
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"vshl", "u", int_arm_neon_vshiftu>;
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// VSHL : Vector Shift Left (Immediate)
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defm VSHLi : N2VSh_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl,
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N2RegVShLFrm>;
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