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Refactor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129938 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -383,6 +383,9 @@ namespace llvm {
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/// encoding specified.
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virtual unsigned getISAEncoding() { return 0; }
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/// EmitDwarfRegOp - Emit dwarf register operation.
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virtual void EmitDwarfRegOp(const MachineLocation &MLoc) const;
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//===------------------------------------------------------------------===//
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// Dwarf Lowering Routines
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//===------------------------------------------------------------------===//
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@ -752,6 +752,40 @@ getDebugValueLocation(const MachineInstr *MI) const {
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return MachineLocation();
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}
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/// EmitDwarfRegOp - Emit dwarf register operation.
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void AsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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unsigned Reg = RI->getDwarfRegNum(MLoc.getReg(), false);
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if (int Offset = MLoc.getOffset()) {
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// If the value is at a certain offset from frame register then
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// use DW_OP_fbreg.
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unsigned OffsetSize = Offset ? MCAsmInfo::getSLEB128Size(Offset) : 1;
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OutStreamer.AddComment("Loc expr size");
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EmitInt16(1 + OffsetSize);
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OutStreamer.AddComment(
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dwarf::OperationEncodingString(dwarf::DW_OP_fbreg));
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EmitInt8(dwarf::DW_OP_fbreg);
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OutStreamer.AddComment("Offset");
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EmitSLEB128(Offset);
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} else {
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if (Reg < 32) {
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OutStreamer.AddComment("Loc expr size");
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EmitInt16(1);
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OutStreamer.AddComment(
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dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg));
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EmitInt8(dwarf::DW_OP_reg0 + Reg);
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} else {
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OutStreamer.AddComment("Loc expr size");
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EmitInt16(1 + MCAsmInfo::getULEB128Size(Reg));
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OutStreamer.AddComment(
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dwarf::OperationEncodingString(dwarf::DW_OP_regx));
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EmitInt8(dwarf::DW_OP_regx);
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OutStreamer.AddComment(Twine(Reg));
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EmitULEB128(Reg);
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}
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}
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}
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bool AsmPrinter::doFinalization(Module &M) {
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// Emit global variables.
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for (Module::const_global_iterator I = M.global_begin(), E = M.global_end();
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@ -2692,36 +2692,7 @@ void DwarfDebug::emitDebugLoc() {
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} else {
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Asm->OutStreamer.EmitSymbolValue(Entry.Begin, Size, 0);
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Asm->OutStreamer.EmitSymbolValue(Entry.End, Size, 0);
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const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo();
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unsigned Reg = RI->getDwarfRegNum(Entry.Loc.getReg(), false);
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if (int Offset = Entry.Loc.getOffset()) {
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// If the value is at a certain offset from frame register then
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// use DW_OP_fbreg.
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unsigned OffsetSize = Offset ? MCAsmInfo::getSLEB128Size(Offset) : 1;
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Asm->OutStreamer.AddComment("Loc expr size");
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Asm->EmitInt16(1 + OffsetSize);
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Asm->OutStreamer.AddComment(
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dwarf::OperationEncodingString(dwarf::DW_OP_fbreg));
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Asm->EmitInt8(dwarf::DW_OP_fbreg);
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Asm->OutStreamer.AddComment("Offset");
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Asm->EmitSLEB128(Offset);
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} else {
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if (Reg < 32) {
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Asm->OutStreamer.AddComment("Loc expr size");
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Asm->EmitInt16(1);
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Asm->OutStreamer.AddComment(
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dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg));
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Asm->EmitInt8(dwarf::DW_OP_reg0 + Reg);
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} else {
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Asm->OutStreamer.AddComment("Loc expr size");
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Asm->EmitInt16(1 + MCAsmInfo::getULEB128Size(Reg));
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Asm->OutStreamer.AddComment(
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dwarf::OperationEncodingString(dwarf::DW_OP_regx));
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Asm->EmitInt8(dwarf::DW_OP_regx);
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Asm->OutStreamer.AddComment(Twine(Reg));
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Asm->EmitULEB128(Reg);
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}
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}
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Asm->EmitDwarfRegOp(Entry.Loc);
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}
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}
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}
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