Refactor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129938 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Devang Patel 2011-04-21 21:07:35 +00:00
parent 8859df5911
commit acc381bee9
3 changed files with 38 additions and 30 deletions

View File

@ -383,6 +383,9 @@ namespace llvm {
/// encoding specified.
virtual unsigned getISAEncoding() { return 0; }
/// EmitDwarfRegOp - Emit dwarf register operation.
virtual void EmitDwarfRegOp(const MachineLocation &MLoc) const;
//===------------------------------------------------------------------===//
// Dwarf Lowering Routines
//===------------------------------------------------------------------===//

View File

@ -752,6 +752,40 @@ getDebugValueLocation(const MachineInstr *MI) const {
return MachineLocation();
}
/// EmitDwarfRegOp - Emit dwarf register operation.
void AsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
const TargetRegisterInfo *RI = TM.getRegisterInfo();
unsigned Reg = RI->getDwarfRegNum(MLoc.getReg(), false);
if (int Offset = MLoc.getOffset()) {
// If the value is at a certain offset from frame register then
// use DW_OP_fbreg.
unsigned OffsetSize = Offset ? MCAsmInfo::getSLEB128Size(Offset) : 1;
OutStreamer.AddComment("Loc expr size");
EmitInt16(1 + OffsetSize);
OutStreamer.AddComment(
dwarf::OperationEncodingString(dwarf::DW_OP_fbreg));
EmitInt8(dwarf::DW_OP_fbreg);
OutStreamer.AddComment("Offset");
EmitSLEB128(Offset);
} else {
if (Reg < 32) {
OutStreamer.AddComment("Loc expr size");
EmitInt16(1);
OutStreamer.AddComment(
dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg));
EmitInt8(dwarf::DW_OP_reg0 + Reg);
} else {
OutStreamer.AddComment("Loc expr size");
EmitInt16(1 + MCAsmInfo::getULEB128Size(Reg));
OutStreamer.AddComment(
dwarf::OperationEncodingString(dwarf::DW_OP_regx));
EmitInt8(dwarf::DW_OP_regx);
OutStreamer.AddComment(Twine(Reg));
EmitULEB128(Reg);
}
}
}
bool AsmPrinter::doFinalization(Module &M) {
// Emit global variables.
for (Module::const_global_iterator I = M.global_begin(), E = M.global_end();

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@ -2692,36 +2692,7 @@ void DwarfDebug::emitDebugLoc() {
} else {
Asm->OutStreamer.EmitSymbolValue(Entry.Begin, Size, 0);
Asm->OutStreamer.EmitSymbolValue(Entry.End, Size, 0);
const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo();
unsigned Reg = RI->getDwarfRegNum(Entry.Loc.getReg(), false);
if (int Offset = Entry.Loc.getOffset()) {
// If the value is at a certain offset from frame register then
// use DW_OP_fbreg.
unsigned OffsetSize = Offset ? MCAsmInfo::getSLEB128Size(Offset) : 1;
Asm->OutStreamer.AddComment("Loc expr size");
Asm->EmitInt16(1 + OffsetSize);
Asm->OutStreamer.AddComment(
dwarf::OperationEncodingString(dwarf::DW_OP_fbreg));
Asm->EmitInt8(dwarf::DW_OP_fbreg);
Asm->OutStreamer.AddComment("Offset");
Asm->EmitSLEB128(Offset);
} else {
if (Reg < 32) {
Asm->OutStreamer.AddComment("Loc expr size");
Asm->EmitInt16(1);
Asm->OutStreamer.AddComment(
dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg));
Asm->EmitInt8(dwarf::DW_OP_reg0 + Reg);
} else {
Asm->OutStreamer.AddComment("Loc expr size");
Asm->EmitInt16(1 + MCAsmInfo::getULEB128Size(Reg));
Asm->OutStreamer.AddComment(
dwarf::OperationEncodingString(dwarf::DW_OP_regx));
Asm->EmitInt8(dwarf::DW_OP_regx);
Asm->OutStreamer.AddComment(Twine(Reg));
Asm->EmitULEB128(Reg);
}
}
Asm->EmitDwarfRegOp(Entry.Loc);
}
}
}