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Teach the scheduler to emit the appropriate INLINEASM MachineInstr for an
ISD::INLINEASM node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25668 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -283,6 +283,35 @@ void ScheduleDAG::EmitNode(NodeInfo *NI) {
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MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC);
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break;
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}
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case ISD::INLINEASM: {
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unsigned NumOps = Node->getNumOperands();
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if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
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--NumOps; // Ignore the flag operand.
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// Create the inline asm machine instruction.
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MachineInstr *MI =
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new MachineInstr(BB, TargetInstrInfo::INLINEASM, (NumOps-2)/2+1);
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// Add the asm string as an external symbol operand.
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const char *AsmStr =
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cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
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MI->addExternalSymbolOperand(AsmStr, false);
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// Add all of the operand registers to the instruction.
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for (unsigned i = 2; i != NumOps; i += 2) {
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unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
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unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
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MachineOperand::UseType UseTy;
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switch (Flags) {
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default: assert(0 && "Bad flags!");
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case 1: UseTy = MachineOperand::Use; break;
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case 2: UseTy = MachineOperand::Def; break;
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case 3: UseTy = MachineOperand::UseAndDef; break;
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}
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MI->addMachineRegOperand(Reg, UseTy);
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}
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break;
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}
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}
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}
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