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Teach the scheduler to emit the appropriate INLINEASM MachineInstr for an

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ISD::INLINEASM node.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25668 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-01-26 23:28:04 +00:00
parent 4ed88eb822
commit acc43bf4ab
1 changed files with 29 additions and 0 deletions
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29
lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
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@ -283,6 +283,35 @@ void ScheduleDAG::EmitNode(NodeInfo *NI) {
MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC);
break;
}
case ISD::INLINEASM: {
unsigned NumOps = Node->getNumOperands();
if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
--NumOps; // Ignore the flag operand.
// Create the inline asm machine instruction.
MachineInstr *MI =
new MachineInstr(BB, TargetInstrInfo::INLINEASM, (NumOps-2)/2+1);
// Add the asm string as an external symbol operand.
const char *AsmStr =
cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
MI->addExternalSymbolOperand(AsmStr, false);
// Add all of the operand registers to the instruction.
for (unsigned i = 2; i != NumOps; i += 2) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
unsigned Flags = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
MachineOperand::UseType UseTy;
switch (Flags) {
default: assert(0 && "Bad flags!");
case 1: UseTy = MachineOperand::Use; break;
case 2: UseTy = MachineOperand::Def; break;
case 3: UseTy = MachineOperand::UseAndDef; break;
}
MI->addMachineRegOperand(Reg, UseTy);
}
break;
}
}
}