6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-18 13:34:04 +00:00
Code Issues Projects Releases Wiki Activity

expand a note

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41021 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-08-11 18:19:07 +00:00
parent 384f4a94f8
commit ace2e8ad0c
1 changed files with 22 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
lib/Target/X86/README.txt
View File

@ -559,7 +559,25 @@ shorter than movl + leal.
//===---------------------------------------------------------------------===//
Implement CTTZ, CTLZ with bsf and bsr.
Implement CTTZ, CTLZ with bsf and bsr. GCC produces:
int ctz_(unsigned X) { return __builtin_ctz(X); }
int clz_(unsigned X) { return __builtin_clz(X); }
int ffs_(unsigned X) { return __builtin_ffs(X); }
_ctz_:
bsfl 4(%esp), %eax
ret
_clz_:
bsrl 4(%esp), %eax
xorl $31, %eax
ret
_ffs_:
movl $-1, %edx
bsfl 4(%esp), %eax
cmove %edx, %eax
addl $1, %eax
ret
//===---------------------------------------------------------------------===//
@ -1077,8 +1095,9 @@ This is a "commutable two-address" register coallescing deficiency:
define <4 x float> @test1(<4 x float> %V) {
entry:
%tmp8 = shufflevector <4 x float> %V, <4 x float> undef, <4 x i32> < i32 3, i32 2, i32 1, i32 0 > ; <<4 x float>> [#uses=1]
%add = add <4 x float> %tmp8, %V ; <<4 x float>> [#uses=1]
%tmp8 = shufflevector <4 x float> %V, <4 x float> undef,
<4 x i32> < i32 3, i32 2, i32 1, i32 0 >
%add = add <4 x float> %tmp8, %V
ret <4 x float> %add
}