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X86: If SSE4.1 is missing lower SMUL_LOHI of v4i32 to pmuludq and fix up the high parts.
This is more expensive than pmuldq but still cheaper than scalarizing the whole thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207370 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer
parent
75955d843f
commit
ad1f916eaf
@ -941,6 +941,7 @@ void X86TargetLowering::resetOperationActions() {
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setOperationAction(ISD::MUL, MVT::v4i32, Custom);
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setOperationAction(ISD::MUL, MVT::v2i64, Custom);
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setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
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setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
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setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
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setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
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setOperationAction(ISD::SUB, MVT::v16i8, Legal);
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@ -1062,7 +1063,6 @@ void X86TargetLowering::resetOperationActions() {
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// FIXME: Do we need to handle scalar-to-vector here?
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setOperationAction(ISD::MUL, MVT::v4i32, Legal);
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setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
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setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
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setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
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@ -13166,8 +13166,9 @@ static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
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// Emit two multiplies, one for the lower 2 ints and one for the higher 2
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// ints.
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MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
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bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
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unsigned Opcode =
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Op->getOpcode() == ISD::UMUL_LOHI ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
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(!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
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SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
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DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
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SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
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@ -13179,6 +13180,20 @@ static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
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const int LowMask[] = {0, 4, 2, 6, 8, 12, 10, 14};
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SDValue Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
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// If we have a signed multiply but no PMULDQ fix up the high parts of a
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// unsigned multiply.
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if (IsSigned && !Subtarget->hasSSE41()) {
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SDValue ShAmt =
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DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
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SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
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DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
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SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
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DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
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SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
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Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
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}
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return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getValueType(), Highs, Lows);
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}
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@ -1,19 +1,20 @@
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; RUN: llc -march=x86-64 -mcpu=corei7 < %s | FileCheck %s -check-prefix=SSE
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; RUN: llc -march=x86-64 -mcpu=core2 -mattr=+sse4.1 < %s | FileCheck %s -check-prefix=SSE41
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; RUN: llc -march=x86-64 -mcpu=core2 < %s | FileCheck %s -check-prefix=SSE
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; RUN: llc -march=x86-64 -mcpu=core-avx2 < %s | FileCheck %s -check-prefix=AVX
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define <4 x i32> @test1(<4 x i32> %a) {
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%div = udiv <4 x i32> %a, <i32 7, i32 7, i32 7, i32 7>
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ret <4 x i32> %div
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; SSE-LABEL: test1:
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; SSE: pmuludq
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; SSE: pshufd $57
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; SSE: pmuludq
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; SSE: shufps $-35
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; SSE: psubd
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; SSE: psrld $1
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; SSE: padd
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; SSE: psrld $2
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; SSE41-LABEL: test1:
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; SSE41: pmuludq
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; SSE41: pshufd $57
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; SSE41: pmuludq
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; SSE41: shufps $-35
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; SSE41: psubd
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; SSE41: psrld $1
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; SSE41: padd
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; SSE41: psrld $2
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; AVX-LABEL: test1:
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; AVX: vpmuludq
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@ -46,12 +47,12 @@ define <8 x i16> @test3(<8 x i16> %a) {
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%div = udiv <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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ret <8 x i16> %div
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; SSE-LABEL: test3:
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; SSE: pmulhuw
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; SSE: psubw
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; SSE: psrlw $1
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; SSE: paddw
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; SSE: psrlw $2
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; SSE41-LABEL: test3:
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; SSE41: pmulhuw
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; SSE41: psubw
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; SSE41: psrlw $1
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; SSE41: paddw
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; SSE41: psrlw $2
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; AVX-LABEL: test3:
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; AVX: vpmulhuw
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@ -78,11 +79,11 @@ define <8 x i16> @test5(<8 x i16> %a) {
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%div = sdiv <8 x i16> %a, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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ret <8 x i16> %div
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; SSE-LABEL: test5:
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; SSE: pmulhw
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; SSE: psrlw $15
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; SSE: psraw $1
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; SSE: paddw
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; SSE41-LABEL: test5:
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; SSE41: pmulhw
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; SSE41: psrlw $15
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; SSE41: psraw $1
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; SSE41: paddw
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; AVX-LABEL: test5:
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; AVX: vpmulhw
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@ -112,13 +113,29 @@ define <4 x i32> @test8(<4 x i32> %a) {
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%div = sdiv <4 x i32> %a, <i32 7, i32 7, i32 7, i32 7>
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ret <4 x i32> %div
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; SSE41-LABEL: test8:
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; SSE41: pmuldq
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; SSE41: pshufd $57
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; SSE41-NOT: pshufd $57
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; SSE41: pmuldq
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; SSE41: shufps $-35
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; SSE41: pshufd $-40
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; SSE41: padd
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; SSE41: psrld $31
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; SSE41: psrad $2
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; SSE41: padd
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; SSE-LABEL: test8:
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; SSE: pmuldq
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; SSE: psrad $31
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; SSE: pand
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; SSE: paddd
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; SSE: pmuludq
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; SSE: pshufd $57
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; SSE-NOT: pshufd $57
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; SSE: pmuldq
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; SSE: pmuludq
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; SSE: shufps $-35
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; SSE: pshufd $-40
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; SSE: psubd
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; SSE: padd
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; SSE: psrld $31
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; SSE: psrad $2
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