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https://github.com/c64scene-ar/llvm-6502.git
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[SystemZ] Add immediate addition involving high words
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191774 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford
parent
bd1958d8e9
commit
ad366a3f67
@ -1386,6 +1386,25 @@ class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
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let Constraints = "$R1 = $R1src";
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}
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// Like BinaryRIE, but expanded after RA depending on the choice of register.
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class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls,
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Immediate imm>
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: Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
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[(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
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// Like BinaryRIAndK, but expanded after RA depending on the choice of register.
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multiclass BinaryRIAndKPseudo<string key, SDPatternOperator operator,
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RegisterOperand cls, Immediate imm> {
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let NumOpsKey = key in {
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let NumOpsValue = "3" in
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def K : BinaryRIEPseudo<null_frag, cls, imm>,
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Requires<[FeatureHighWord, FeatureDistinctOps]>;
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let NumOpsValue = "2", isConvertibleToThreeAddress = 1 in
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def "" : BinaryRIPseudo<operator, cls, imm>,
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Requires<[FeatureHighWord]>;
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}
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}
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// Like CompareRI, but expanded after RA depending on the choice of register.
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class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
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Immediate imm>
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@ -107,6 +107,28 @@ void SystemZInstrInfo::expandRIPseudo(MachineInstr *MI, unsigned LowOpcode,
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MI->getOperand(1).setImm(uint32_t(MI->getOperand(1).getImm()));
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}
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// MI is a three-operand RIE-style pseudo instruction. Replace it with
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// LowOpcode3 if the registers are both low GR32s, otherwise use a move
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// followed by HighOpcode or LowOpcode, depending on whether the target
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// is a high or low GR32.
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void SystemZInstrInfo::expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode,
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unsigned LowOpcodeK,
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unsigned HighOpcode) const {
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unsigned DestReg = MI->getOperand(0).getReg();
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unsigned SrcReg = MI->getOperand(1).getReg();
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bool DestIsHigh = isHighReg(DestReg);
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bool SrcIsHigh = isHighReg(SrcReg);
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if (!DestIsHigh && !SrcIsHigh)
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MI->setDesc(get(LowOpcodeK));
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else {
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emitGRX32Move(*MI->getParent(), MI, MI->getDebugLoc(),
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DestReg, SrcReg, SystemZ::LR, 32,
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MI->getOperand(1).isKill());
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MI->setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
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MI->getOperand(1).setReg(DestReg);
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}
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}
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// MI is an RXY-style pseudo instruction. Replace it with LowOpcode
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// if the first operand is a low GR32 and HighOpcode if the first operand
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// is a high GR32.
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@ -651,6 +673,7 @@ SystemZInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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LiveVariables *LV) const {
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MachineInstr *MI = MBBI;
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MachineBasicBlock *MBB = MI->getParent();
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MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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unsigned Opcode = MI->getOpcode();
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unsigned NumOps = MI->getNumOperands();
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@ -660,10 +683,23 @@ SystemZInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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// because it tends to be shorter and because some instructions
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// have memory forms that can be used during spilling.
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if (TM.getSubtargetImpl()->hasDistinctOps()) {
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int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
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if (ThreeOperandOpcode >= 0) {
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MachineOperand &Dest = MI->getOperand(0);
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MachineOperand &Src = MI->getOperand(1);
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unsigned DestReg = Dest.getReg();
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unsigned SrcReg = Src.getReg();
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// AHIMux is only really a three-operand instruction when both operands
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// are low registers. Try to constrain both operands to be low if
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// possible.
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if (Opcode == SystemZ::AHIMux &&
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TargetRegisterInfo::isVirtualRegister(DestReg) &&
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TargetRegisterInfo::isVirtualRegister(SrcReg) &&
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MRI.getRegClass(DestReg)->contains(SystemZ::R1L) &&
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MRI.getRegClass(SrcReg)->contains(SystemZ::R1L)) {
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MRI.constrainRegClass(DestReg, &SystemZ::GR32BitRegClass);
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MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass);
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}
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int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
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if (ThreeOperandOpcode >= 0) {
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MachineInstrBuilder MIB =
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BuildMI(*MBB, MBBI, MI->getDebugLoc(), get(ThreeOperandOpcode))
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.addOperand(Dest);
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@ -918,6 +954,18 @@ SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
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return true;
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case SystemZ::AHIMux:
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expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
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return true;
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case SystemZ::AHIMuxK:
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expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
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return true;
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case SystemZ::AFIMux:
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expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
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return true;
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case SystemZ::RISBMux: {
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bool DestIsHigh = isHighReg(MI->getOperand(0).getReg());
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bool SrcIsHigh = isHighReg(MI->getOperand(2).getReg());
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@ -118,6 +118,8 @@ class SystemZInstrInfo : public SystemZGenInstrInfo {
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void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
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void expandRIPseudo(MachineInstr *MI, unsigned LowOpcode,
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unsigned HighOpcode, bool ConvertHigh) const;
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void expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode,
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unsigned LowOpcodeK, unsigned HighOpcode) const;
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void expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode,
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unsigned HighOpcode) const;
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void expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode,
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@ -685,11 +685,16 @@ let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
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def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
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// Addition of signed 16-bit immediates.
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defm AHIMux : BinaryRIAndKPseudo<"ahimux", add, GRX32, imm32sx16>;
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defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, add, GR32, imm32sx16>;
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defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>;
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// Addition of signed 32-bit immediates.
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def AFIMux : BinaryRIPseudo<add, GRX32, simm32>,
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Requires<[FeatureHighWord]>;
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def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>;
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def AIH : BinaryRIL<"aih", 0xCC8, add, GRH32, simm32>,
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Requires<[FeatureHighWord]>;
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def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;
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// Addition of memory.
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@ -554,3 +554,118 @@ define i32 @f25(i32 %old) {
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"=r,h,h"(i32 %sel3, i32 %sel4)
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ret i32 %res2
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}
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; Test two-operand halfword immediate addition involving high registers.
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define void @f26() {
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; CHECK-LABEL: f26:
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; CHECK: stepa [[REG:%r[0-5]]]
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; CHECK: aih [[REG]], -32768
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; CHECK: stepb [[REG]]
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; CHECK: aih [[REG]], 1
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; CHECK: stepc [[REG]]
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; CHECK: aih [[REG]], 32767
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; CHECK: stepd [[REG]]
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; CHECK: br %r14
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%res1 = call i32 asm "stepa $0", "=h"()
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%add1 = add i32 %res1, -32768
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%res2 = call i32 asm "stepb $0, $1", "=h,h"(i32 %add1)
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%add2 = add i32 %res2, 1
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%res3 = call i32 asm "stepc $0, $1", "=h,h"(i32 %add2)
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%add3 = add i32 %res3, 32767
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call void asm sideeffect "stepd $0", "h"(i32 %add3)
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ret void
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}
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; Test two-operand halfword immediate addition involving low registers.
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define void @f27() {
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; CHECK-LABEL: f27:
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; CHECK: stepa [[REG:%r[0-5]]]
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; CHECK: ahi [[REG]], -32768
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; CHECK: stepb [[REG]]
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; CHECK: ahi [[REG]], 1
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; CHECK: stepc [[REG]]
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; CHECK: ahi [[REG]], 32767
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; CHECK: stepd [[REG]]
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; CHECK: br %r14
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%res1 = call i32 asm "stepa $0", "=r"()
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%add1 = add i32 %res1, -32768
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%res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %add1)
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%add2 = add i32 %res2, 1
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%res3 = call i32 asm "stepc $0, $1", "=r,r"(i32 %add2)
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%add3 = add i32 %res3, 32767
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call void asm sideeffect "stepd $0", "r"(i32 %add3)
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ret void
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}
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; Test three-operand halfword immediate addition involving mixtures of low
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; and high registers. RISBHG/AIH would be OK too, instead of AHIK/RISBHG.
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define i32 @f28(i32 %old) {
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; CHECK-LABEL: f28:
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; CHECK: ahik [[REG1:%r[0-5]]], %r2, 14
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; CHECK: stepa %r2, [[REG1]]
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; CHECK: ahik [[TMP:%r[0-5]]], [[REG1]], 254
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; CHECK: risbhg [[REG2:%r[0-5]]], [[TMP]], 0, 159, 32
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; CHECK: stepb [[REG1]], [[REG2]]
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; CHECK: risbhg [[REG3:%r[0-5]]], [[REG2]], 0, 159, 0
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; CHECK: aih [[REG3]], 127
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; CHECK: stepc [[REG2]], [[REG3]]
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; CHECK: risblg %r2, [[REG3]], 0, 159, 32
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; CHECK: ahi %r2, 128
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; CHECK: stepd [[REG3]], %r2
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; CHECK: br %r14
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%add1 = add i32 %old, 14
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%res1 = call i32 asm "stepa $1, $2",
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"=r,r,0"(i32 %old, i32 %add1)
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%add2 = add i32 %res1, 254
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%res2 = call i32 asm "stepb $1, $2",
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"=h,r,0"(i32 %res1, i32 %add2)
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%add3 = add i32 %res2, 127
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%res3 = call i32 asm "stepc $1, $2",
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"=h,h,0"(i32 %res2, i32 %add3)
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%add4 = add i32 %res3, 128
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%res4 = call i32 asm "stepd $1, $2",
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"=r,h,0"(i32 %res3, i32 %add4)
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ret i32 %res4
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}
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; Test large immediate addition involving high registers.
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define void @f29() {
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; CHECK-LABEL: f29:
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; CHECK: stepa [[REG:%r[0-5]]]
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; CHECK: aih [[REG]], -32769
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; CHECK: stepb [[REG]]
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; CHECK: aih [[REG]], 32768
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; CHECK: stepc [[REG]]
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; CHECK: aih [[REG]], 1000000000
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; CHECK: stepd [[REG]]
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; CHECK: br %r14
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%res1 = call i32 asm "stepa $0", "=h"()
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%add1 = add i32 %res1, -32769
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%res2 = call i32 asm "stepb $0, $1", "=h,h"(i32 %add1)
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%add2 = add i32 %res2, 32768
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%res3 = call i32 asm "stepc $0, $1", "=h,h"(i32 %add2)
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%add3 = add i32 %res3, 1000000000
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call void asm sideeffect "stepd $0", "h"(i32 %add3)
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ret void
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}
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; Test large immediate addition involving low registers.
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define void @f30() {
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; CHECK-LABEL: f30:
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; CHECK: stepa [[REG:%r[0-5]]]
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; CHECK: afi [[REG]], -32769
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; CHECK: stepb [[REG]]
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; CHECK: afi [[REG]], 32768
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; CHECK: stepc [[REG]]
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; CHECK: afi [[REG]], 1000000000
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; CHECK: stepd [[REG]]
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; CHECK: br %r14
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%res1 = call i32 asm "stepa $0", "=r"()
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%add1 = add i32 %res1, -32769
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%res2 = call i32 asm "stepb $0, $1", "=r,r"(i32 %add1)
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%add2 = add i32 %res2, 32768
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%res3 = call i32 asm "stepc $0, $1", "=r,r"(i32 %add2)
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%add3 = add i32 %res3, 1000000000
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call void asm sideeffect "stepd $0", "r"(i32 %add3)
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ret void
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}
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@ -349,6 +349,24 @@
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# CHECK: ahy %r15, 0
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0xe3 0xf0 0x00 0x00 0x00 0x7a
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# CHECK: aih %r0, -2147483648
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0xcc 0x08 0x80 0x00 0x00 0x00
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# CHECK: aih %r0, -1
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0xcc 0x08 0xff 0xff 0xff 0xff
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# CHECK: aih %r0, 0
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0xcc 0x08 0x00 0x00 0x00 0x00
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# CHECK: aih %r0, 1
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0xcc 0x08 0x00 0x00 0x00 0x01
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# CHECK: aih %r0, 2147483647
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0xcc 0x08 0x7f 0xff 0xff 0xff
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# CHECK: aih %r15, 0
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0xcc 0xf8 0x00 0x00 0x00 0x00
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# CHECK: alcgr %r0, %r0
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0xb9 0x88 0x00 0x00
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@ -24,6 +24,14 @@
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ahik %r0, %r1, 32768
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ahik %r0, %r1, foo
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#CHECK: error: invalid operand
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#CHECK: aih %r0, (-1 << 31) - 1
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#CHECK: error: invalid operand
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#CHECK: aih %r0, (1 << 31)
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aih %r0, (-1 << 31) - 1
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aih %r0, (1 << 31)
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#CHECK: error: invalid operand
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#CHECK: fidbra %f0, 0, %f0, -1
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#CHECK: error: invalid operand
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@ -128,6 +128,11 @@
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ahy %r0, -524289
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ahy %r0, 524288
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#CHECK: error: {{(instruction requires: high-word)?}}
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#CHECK: aih %r0, 0
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aih %r0, 0
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#CHECK: error: invalid operand
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#CHECK: al %r0, -1
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#CHECK: error: invalid operand
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@ -49,6 +49,20 @@
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ahik %r15, %r0, 0
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ahik %r7, %r8, -16
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#CHECK: aih %r0, -2147483648 # encoding: [0xcc,0x08,0x80,0x00,0x00,0x00]
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#CHECK: aih %r0, -1 # encoding: [0xcc,0x08,0xff,0xff,0xff,0xff]
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#CHECK: aih %r0, 0 # encoding: [0xcc,0x08,0x00,0x00,0x00,0x00]
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#CHECK: aih %r0, 1 # encoding: [0xcc,0x08,0x00,0x00,0x00,0x01]
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#CHECK: aih %r0, 2147483647 # encoding: [0xcc,0x08,0x7f,0xff,0xff,0xff]
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#CHECK: aih %r15, 0 # encoding: [0xcc,0xf8,0x00,0x00,0x00,0x00]
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aih %r0, -1 << 31
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aih %r0, -1
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aih %r0, 0
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aih %r0, 1
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aih %r0, (1 << 31) - 1
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aih %r15, 0
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#CHECK: alghsik %r0, %r0, -32768 # encoding: [0xec,0x00,0x80,0x00,0x00,0xdb]
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#CHECK: alghsik %r0, %r0, -1 # encoding: [0xec,0x00,0xff,0xff,0x00,0xdb]
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#CHECK: alghsik %r0, %r0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0xdb]
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