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Refactor isConsecutiveLoad from X86 to TargetLowering so DAG combiner can make use of it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50991 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -19,6 +19,7 @@
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/GlobalVariable.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/STLExtras.h"
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@ -1478,6 +1479,73 @@ TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
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return SDOperand();
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}
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/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
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/// node is a GlobalAddress + offset.
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bool TargetLowering::isGAPlusOffset(SDNode *N, GlobalValue* &GA,
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int64_t &Offset) const {
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if (isa<GlobalAddressSDNode>(N)) {
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GA = cast<GlobalAddressSDNode>(N)->getGlobal();
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return true;
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}
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if (N->getOpcode() == ISD::ADD) {
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SDOperand N1 = N->getOperand(0);
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SDOperand N2 = N->getOperand(1);
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if (isGAPlusOffset(N1.Val, GA, Offset)) {
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ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
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if (V) {
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Offset += V->getSignExtended();
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return true;
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}
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} else if (isGAPlusOffset(N2.Val, GA, Offset)) {
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ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
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if (V) {
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Offset += V->getSignExtended();
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return true;
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}
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}
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}
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return false;
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}
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/// isConsecutiveLoad - Return true if LD (which must be a LoadSDNode) is
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/// loading 'Bytes' bytes from a location that is 'Dist' units away from the
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/// location that the 'Base' load is loading from.
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bool TargetLowering::isConsecutiveLoad(SDNode *LD, SDNode *Base,
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unsigned Bytes, int Dist,
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MachineFrameInfo *MFI) const {
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if (LD->getOperand(0).Val != Base->getOperand(0).Val)
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return false;
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MVT::ValueType VT = LD->getValueType(0);
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if (MVT::getSizeInBits(VT) / 8 != Bytes)
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return false;
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SDOperand Loc = LD->getOperand(1);
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SDOperand BaseLoc = Base->getOperand(1);
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if (Loc.getOpcode() == ISD::FrameIndex) {
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if (BaseLoc.getOpcode() != ISD::FrameIndex)
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return false;
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int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
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int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
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int FS = MFI->getObjectSize(FI);
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int BFS = MFI->getObjectSize(BFI);
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if (FS != BFS || FS != (int)Bytes) return false;
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return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
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}
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GlobalValue *GV1 = NULL;
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GlobalValue *GV2 = NULL;
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int64_t Offset1 = 0;
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int64_t Offset2 = 0;
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bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
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bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
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if (isGA1 && isGA2 && GV1 == GV2)
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return Offset1 == (Offset2 + Dist*Bytes);
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return false;
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}
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SDOperand TargetLowering::
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PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
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// Default implementation: no optimization.
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@ -6194,71 +6194,23 @@ static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
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}
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/// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
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/// node is a GlobalAddress + an offset.
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static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
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unsigned Opc = N->getOpcode();
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if (Opc == X86ISD::Wrapper) {
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if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
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/// node is a GlobalAddress + offset.
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bool X86TargetLowering::isGAPlusOffset(SDNode *N,
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GlobalValue* &GA, int64_t &Offset) const{
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if (N->getOpcode() == X86ISD::Wrapper) {
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if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
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GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
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return true;
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}
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} else if (Opc == ISD::ADD) {
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SDOperand N1 = N->getOperand(0);
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SDOperand N2 = N->getOperand(1);
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if (isGAPlusOffset(N1.Val, GA, Offset)) {
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ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
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if (V) {
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Offset += V->getSignExtended();
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return true;
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}
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} else if (isGAPlusOffset(N2.Val, GA, Offset)) {
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ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
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if (V) {
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Offset += V->getSignExtended();
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return true;
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}
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}
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}
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return false;
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return TargetLowering::isGAPlusOffset(N, GA, Offset);
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}
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/// isConsecutiveLoad - Returns true if N is loading from an address of Base
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/// + Dist * Size.
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static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size,
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MachineFrameInfo *MFI) {
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if (N->getOperand(0).Val != Base->getOperand(0).Val)
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return false;
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SDOperand Loc = N->getOperand(1);
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SDOperand BaseLoc = Base->getOperand(1);
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if (Loc.getOpcode() == ISD::FrameIndex) {
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if (BaseLoc.getOpcode() != ISD::FrameIndex)
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return false;
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int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
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int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
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int FS = MFI->getObjectSize(FI);
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int BFS = MFI->getObjectSize(BFI);
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if (FS != BFS || FS != Size) return false;
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return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size);
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} else {
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GlobalValue *GV1 = NULL;
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GlobalValue *GV2 = NULL;
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int64_t Offset1 = 0;
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int64_t Offset2 = 0;
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bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
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bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
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if (isGA1 && isGA2 && GV1 == GV2)
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return Offset1 == (Offset2 + Dist*Size);
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}
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return false;
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}
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static bool isBaseAlignmentOfN(unsigned N, SDNode *Base, MachineFrameInfo *MFI,
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const X86Subtarget *Subtarget) {
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static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
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const TargetLowering &TLI) {
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GlobalValue *GV;
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int64_t Offset = 0;
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if (isGAPlusOffset(Base, GV, Offset))
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if (TLI.isGAPlusOffset(Base, GV, Offset))
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return (GV->getAlignment() >= N && (Offset % N) == 0);
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// DAG combine handles the stack object case.
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return false;
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@ -6266,8 +6218,9 @@ static bool isBaseAlignmentOfN(unsigned N, SDNode *Base, MachineFrameInfo *MFI,
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static bool EltsFromConsecutiveLoads(SDNode *N, SDOperand PermMask,
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unsigned NumElems, MVT::ValueType EVT,
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MachineFrameInfo *MFI,
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SelectionDAG &DAG, SDNode *&Base) {
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SDNode *&Base,
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SelectionDAG &DAG, MachineFrameInfo *MFI,
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const TargetLowering &TLI) {
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Base = NULL;
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for (unsigned i = 0; i < NumElems; ++i) {
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SDOperand Idx = PermMask.getOperand(i);
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@ -6291,7 +6244,8 @@ static bool EltsFromConsecutiveLoads(SDNode *N, SDOperand PermMask,
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if (Elt.getOpcode() == ISD::UNDEF)
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continue;
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if (!isConsecutiveLoad(Elt.Val, Base, i, MVT::getSizeInBits(EVT)/8,MFI))
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if (!TLI.isConsecutiveLoad(Elt.Val, Base,
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MVT::getSizeInBits(EVT)/8, i, MFI))
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return false;
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}
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return true;
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@ -6302,18 +6256,19 @@ static bool EltsFromConsecutiveLoads(SDNode *N, SDOperand PermMask,
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/// if the load addresses are consecutive, non-overlapping, and in the right
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/// order.
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static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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const TargetLowering &TLI) {
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MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
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MVT::ValueType VT = N->getValueType(0);
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MVT::ValueType EVT = MVT::getVectorElementType(VT);
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SDOperand PermMask = N->getOperand(2);
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unsigned NumElems = PermMask.getNumOperands();
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SDNode *Base = NULL;
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if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, MFI, DAG, Base))
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if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base,
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DAG, MFI, TLI))
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return SDOperand();
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LoadSDNode *LD = cast<LoadSDNode>(Base);
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if (isBaseAlignmentOfN(16, Base->getOperand(1).Val, MFI, Subtarget))
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if (isBaseAlignmentOfN(16, Base->getOperand(1).Val, TLI))
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return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
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LD->getSrcValueOffset(), LD->isVolatile());
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return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
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@ -6329,7 +6284,8 @@ static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
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}
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static SDOperand PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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const X86Subtarget *Subtarget,
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const TargetLowering &TLI) {
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// Ignore single operand BUILD_VECTOR.
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if (N->getNumOperands() == 1)
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return SDOperand();
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@ -6360,7 +6316,7 @@ static SDOperand PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
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return SDOperand();
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SDNode *NextLD = getBuildPairElt(Pair, 1);
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if (!ISD::isNON_EXTLoad(NextLD) ||
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!isConsecutiveLoad(NextLD, Base, 1, 4/*32 bits*/, MFI))
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!TLI.isConsecutiveLoad(NextLD, Base, 4/*32 bits*/, 1, MFI))
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return SDOperand();
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}
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LoadSDNode *LD = cast<LoadSDNode>(Base);
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@ -6564,8 +6520,9 @@ SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
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SelectionDAG &DAG = DCI.DAG;
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switch (N->getOpcode()) {
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default: break;
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case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, Subtarget);
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case ISD::BUILD_VECTOR: return PerformBuildVectorCombine(N, DAG, Subtarget);
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case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
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case ISD::BUILD_VECTOR:
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return PerformBuildVectorCombine(N, DAG, Subtarget, *this);
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case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
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case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
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case X86ISD::FXOR:
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@ -370,6 +370,9 @@ namespace llvm {
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const SelectionDAG &DAG,
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unsigned Depth = 0) const;
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virtual bool
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isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
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SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
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ConstraintType getConstraintType(const std::string &Constraint) const;
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