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Use a transposed algorithm for handleMove().
Completely update one interval at a time instead of collecting live range fragments to be updated. This avoids building data structures, except for a single SmallPtrSet of updated intervals. Also share code between handleMove() and handleMoveIntoBundle(). Add support for moving dead defs across other live values in the interval. The MI scheduler can do that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165824 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
780c798222
commit
ad5e969ba9
@ -1007,246 +1007,240 @@ private:
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LiveIntervals& LIS;
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const MachineRegisterInfo& MRI;
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const TargetRegisterInfo& TRI;
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SlotIndex OldIdx;
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SlotIndex NewIdx;
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typedef std::pair<LiveInterval*, LiveRange*> IntRangePair;
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typedef DenseSet<IntRangePair> RangeSet;
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struct RegRanges {
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LiveRange* Use;
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LiveRange* EC;
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LiveRange* Dead;
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LiveRange* Def;
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RegRanges() : Use(0), EC(0), Dead(0), Def(0) {}
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};
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typedef DenseMap<unsigned, RegRanges> BundleRanges;
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SmallPtrSet<LiveInterval*, 8> Updated;
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public:
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HMEditor(LiveIntervals& LIS, const MachineRegisterInfo& MRI,
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const TargetRegisterInfo& TRI, SlotIndex NewIdx)
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: LIS(LIS), MRI(MRI), TRI(TRI), NewIdx(NewIdx) {}
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const TargetRegisterInfo& TRI,
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SlotIndex OldIdx, SlotIndex NewIdx)
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: LIS(LIS), MRI(MRI), TRI(TRI), OldIdx(OldIdx), NewIdx(NewIdx) {}
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// Update intervals for all operands of MI from OldIdx to NewIdx.
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// This assumes that MI used to be at OldIdx, and now resides at
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// NewIdx.
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void moveAllRangesFrom(MachineInstr* MI, SlotIndex OldIdx) {
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assert(NewIdx != OldIdx && "No-op move? That's a bit strange.");
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// Collect the operands.
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RangeSet Entering, Internal, Exiting;
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bool hasRegMaskOp = false;
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collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
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// To keep the LiveRanges valid within an interval, move the ranges closest
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// to the destination first. This prevents ranges from overlapping, to that
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// APIs like removeRange still work.
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if (NewIdx < OldIdx) {
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moveAllEnteringFrom(OldIdx, Entering);
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moveAllInternalFrom(OldIdx, Internal);
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moveAllExitingFrom(OldIdx, Exiting);
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}
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else {
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moveAllExitingFrom(OldIdx, Exiting);
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moveAllInternalFrom(OldIdx, Internal);
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moveAllEnteringFrom(OldIdx, Entering);
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}
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if (hasRegMaskOp)
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updateRegMaskSlots(OldIdx);
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#ifndef NDEBUG
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LIValidator validator;
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validator = std::for_each(Entering.begin(), Entering.end(), validator);
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validator = std::for_each(Internal.begin(), Internal.end(), validator);
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validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
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assert(validator.rangesOk() && "moveAllOperandsFrom broke liveness.");
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#endif
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}
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// Update intervals for all operands of MI to refer to BundleStart's
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// SlotIndex.
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void moveAllRangesInto(MachineInstr* MI, MachineInstr* BundleStart) {
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if (MI == BundleStart)
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return; // Bundling instr with itself - nothing to do.
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SlotIndex OldIdx = LIS.getSlotIndexes()->getInstructionIndex(MI);
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assert(LIS.getSlotIndexes()->getInstructionFromIndex(OldIdx) == MI &&
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"SlotIndex <-> Instruction mapping broken for MI");
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// Collect all ranges already in the bundle.
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MachineBasicBlock::instr_iterator BII(BundleStart);
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RangeSet Entering, Internal, Exiting;
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bool hasRegMaskOp = false;
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collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
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assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
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for (++BII; &*BII == MI || BII->isInsideBundle(); ++BII) {
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if (&*BII == MI)
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/// Update all live ranges touched by MI, assuming a move from OldIdx to
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/// NewIdx.
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void updateAllRanges(MachineInstr *MI) {
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DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": " << *MI);
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bool hasRegMask = false;
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for (MIOperands MO(MI); MO.isValid(); ++MO) {
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if (MO->isRegMask())
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hasRegMask = true;
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if (!MO->isReg())
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continue;
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collectRanges(BII, Entering, Internal, Exiting, hasRegMaskOp, NewIdx);
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assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
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// Aggressively clear all kill flags.
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// They are reinserted by VirtRegRewriter.
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if (MO->isUse())
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MO->setIsKill(false);
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unsigned Reg = MO->getReg();
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if (!Reg)
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continue;
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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updateRange(LIS.getInterval(Reg));
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continue;
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}
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// For physregs, only update the regunits that actually have a
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// precomputed live range.
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for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
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if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))
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updateRange(*LI);
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}
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BundleRanges BR = createBundleRanges(Entering, Internal, Exiting);
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Entering.clear();
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Internal.clear();
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Exiting.clear();
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collectRanges(MI, Entering, Internal, Exiting, hasRegMaskOp, OldIdx);
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assert(!hasRegMaskOp && "Can't have RegMask operand in bundle.");
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DEBUG(dbgs() << "Entering: " << Entering.size() << "\n");
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DEBUG(dbgs() << "Internal: " << Internal.size() << "\n");
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DEBUG(dbgs() << "Exiting: " << Exiting.size() << "\n");
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moveAllEnteringFromInto(OldIdx, Entering, BR);
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moveAllInternalFromInto(OldIdx, Internal, BR);
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moveAllExitingFromInto(OldIdx, Exiting, BR);
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#ifndef NDEBUG
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LIValidator validator;
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validator = std::for_each(Entering.begin(), Entering.end(), validator);
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validator = std::for_each(Internal.begin(), Internal.end(), validator);
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validator = std::for_each(Exiting.begin(), Exiting.end(), validator);
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assert(validator.rangesOk() && "moveAllOperandsInto broke liveness.");
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#endif
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if (hasRegMask)
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updateRegMaskSlots();
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}
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private:
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#ifndef NDEBUG
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class LIValidator {
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private:
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DenseSet<const LiveInterval*> Checked, Bogus;
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public:
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void operator()(const IntRangePair& P) {
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const LiveInterval* LI = P.first;
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if (Checked.count(LI))
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return;
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Checked.insert(LI);
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if (LI->empty())
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return;
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SlotIndex LastEnd = LI->begin()->start;
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for (LiveInterval::const_iterator LRI = LI->begin(), LRE = LI->end();
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LRI != LRE; ++LRI) {
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const LiveRange& LR = *LRI;
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if (LastEnd > LR.start || LR.start >= LR.end)
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Bogus.insert(LI);
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LastEnd = LR.end;
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}
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}
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bool rangesOk() const {
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return Bogus.empty();
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}
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};
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#endif
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// Collect IntRangePairs for all operands of MI that may need fixing.
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// Treat's MI's index as OldIdx (regardless of what it is in SlotIndexes'
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// maps).
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void collectRanges(MachineInstr* MI, RangeSet& Entering, RangeSet& Internal,
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RangeSet& Exiting, bool& hasRegMaskOp, SlotIndex OldIdx) {
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hasRegMaskOp = false;
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for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
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MOE = MI->operands_end();
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MOI != MOE; ++MOI) {
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const MachineOperand& MO = *MOI;
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if (MO.isRegMask()) {
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hasRegMaskOp = true;
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continue;
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}
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if (!MO.isReg() || MO.getReg() == 0)
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continue;
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unsigned Reg = MO.getReg();
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// Don't track uses of reserved registers - they're not accurate.
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// Reserved register live ranges look like a set of dead defs.
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bool Resv =
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TargetRegisterInfo::isPhysicalRegister(Reg) && LIS.isReserved(Reg);
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// Collect ranges for register units. These live ranges are computed on
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// demand, so just skip any that haven't been computed yet.
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if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
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if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))
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collectRanges(MO, LI, Entering, Internal, Exiting, OldIdx, Resv);
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} else {
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// Collect ranges for individual virtual registers.
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collectRanges(MO, &LIS.getInterval(Reg),
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Entering, Internal, Exiting, OldIdx);
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}
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}
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}
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void collectRanges(const MachineOperand &MO, LiveInterval *LI,
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RangeSet &Entering, RangeSet &Internal, RangeSet &Exiting,
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SlotIndex OldIdx, bool IgnoreReads = false) {
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if (!IgnoreReads && MO.readsReg()) {
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LiveRange* LR = LI->getLiveRangeContaining(OldIdx);
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if (LR != 0)
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Entering.insert(std::make_pair(LI, LR));
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}
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if (MO.isDef()) {
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LiveRange* LR = LI->getLiveRangeContaining(OldIdx.getRegSlot());
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assert(LR != 0 && "No live range for def?");
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if (LR->end > OldIdx.getDeadSlot())
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Exiting.insert(std::make_pair(LI, LR));
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/// Update a single live range, assuming an instruction has been moved from
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/// OldIdx to NewIdx.
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void updateRange(LiveInterval &LI) {
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if (!Updated.insert(&LI))
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return;
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DEBUG({
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dbgs() << " ";
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if (TargetRegisterInfo::isVirtualRegister(LI.reg))
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dbgs() << PrintReg(LI.reg);
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else
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Internal.insert(std::make_pair(LI, LR));
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}
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dbgs() << PrintRegUnit(LI.reg, &TRI);
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dbgs() << ":\t" << LI << '\n';
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});
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if (SlotIndex::isEarlierInstr(OldIdx, NewIdx))
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handleMoveDown(LI);
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else
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handleMoveUp(LI);
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DEBUG(dbgs() << " -->\t" << LI << '\n');
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LI.verify();
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}
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BundleRanges createBundleRanges(RangeSet& Entering,
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RangeSet& Internal,
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RangeSet& Exiting) {
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BundleRanges BR;
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/// Update LI to reflect an instruction has been moved downwards from OldIdx
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/// to NewIdx.
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///
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/// 1. Live def at OldIdx:
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/// Move def to NewIdx, assert endpoint after NewIdx.
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///
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/// 2. Live def at OldIdx, killed at NewIdx:
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/// Change to dead def at NewIdx.
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/// (Happens when bundling def+kill together).
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///
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/// 3. Dead def at OldIdx:
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/// Move def to NewIdx, possibly across another live value.
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///
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/// 4. Def at OldIdx AND at NewIdx:
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/// Remove live range [OldIdx;NewIdx) and value defined at OldIdx.
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/// (Happens when bundling multiple defs together).
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///
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/// 5. Value read at OldIdx, killed before NewIdx:
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/// Extend kill to NewIdx.
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///
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void handleMoveDown(LiveInterval &LI) {
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// First look for a kill at OldIdx.
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LiveInterval::iterator I = LI.find(OldIdx.getBaseIndex());
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LiveInterval::iterator E = LI.end();
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// Is LI even live at OldIdx?
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if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
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return;
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for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
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EI != EE; ++EI) {
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LiveInterval* LI = EI->first;
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LiveRange* LR = EI->second;
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BR[LI->reg].Use = LR;
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// Handle a live-in value.
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if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
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bool isKill = SlotIndex::isSameInstr(OldIdx, I->end);
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// If the live-in value already extends to NewIdx, there is nothing to do.
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if (!SlotIndex::isEarlierInstr(I->end, NewIdx))
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return;
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// Aggressively remove all kill flags from the old kill point.
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// Kill flags shouldn't be used while live intervals exist, they will be
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// reinserted by VirtRegRewriter.
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if (MachineInstr *KillMI = LIS.getInstructionFromIndex(I->end))
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for (MIBundleOperands MO(KillMI); MO.isValid(); ++MO)
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if (MO->isReg() && MO->isUse())
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MO->setIsKill(false);
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// Adjust I->end to reach NewIdx. This may temporarily make LI invalid by
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// overlapping ranges. Case 5 above.
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I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
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// If this was a kill, there may also be a def. Otherwise we're done.
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if (!isKill)
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return;
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++I;
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}
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for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
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II != IE; ++II) {
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LiveInterval* LI = II->first;
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LiveRange* LR = II->second;
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if (LR->end.isDead()) {
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BR[LI->reg].Dead = LR;
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} else {
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BR[LI->reg].EC = LR;
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// Check for a def at OldIdx.
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if (I == E || !SlotIndex::isSameInstr(OldIdx, I->start))
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return;
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// We have a def at OldIdx.
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VNInfo *DefVNI = I->valno;
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assert(DefVNI->def == I->start && "Inconsistent def");
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DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
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// If the defined value extends beyond NewIdx, just move the def down.
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// This is case 1 above.
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if (SlotIndex::isEarlierInstr(NewIdx, I->end)) {
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I->start = DefVNI->def;
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return;
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}
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// The remaining possibilities are now:
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// 2. Live def at OldIdx, killed at NewIdx: isSameInstr(I->end, NewIdx).
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// 3. Dead def at OldIdx: I->end = OldIdx.getDeadSlot().
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// In either case, it is possible that there is an existing def at NewIdx.
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assert((I->end == OldIdx.getDeadSlot() ||
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SlotIndex::isSameInstr(I->end, NewIdx)) &&
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"Cannot move def below kill");
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LiveInterval::iterator NewI = LI.advanceTo(I, NewIdx.getRegSlot());
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if (NewI != E && SlotIndex::isSameInstr(NewI->start, NewIdx)) {
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// There is an existing def at NewIdx, case 4 above. The def at OldIdx is
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// coalesced into that value.
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assert(NewI->valno != DefVNI && "Multiple defs of value?");
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LI.removeValNo(DefVNI);
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return;
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}
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// There was no existing def at NewIdx. Turn *I into a dead def at NewIdx.
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// If the def at OldIdx was dead, we allow it to be moved across other LI
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// values. The new range should be placed immediately before NewI, move any
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// intermediate ranges up.
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assert(NewI != I && "Inconsistent iterators");
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std::copy(llvm::next(I), NewI, I);
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*llvm::prior(NewI) = LiveRange(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
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}
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/// Update LI to reflect an instruction has been moved upwards from OldIdx
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/// to NewIdx.
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///
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/// 1. Live def at OldIdx:
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/// Hoist def to NewIdx.
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///
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/// 2. Dead def at OldIdx:
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/// Hoist def+end to NewIdx, possibly move across other values.
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///
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/// 3. Dead def at OldIdx AND existing def at NewIdx:
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/// Remove value defined at OldIdx, coalescing it with existing value.
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///
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/// 4. Live def at OldIdx AND existing def at NewIdx:
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/// Remove value defined at NewIdx, hoist OldIdx def to NewIdx.
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/// (Happens when bundling multiple defs together).
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///
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/// 5. Value killed at OldIdx:
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/// Hoist kill to NewIdx, then scan for last kill between NewIdx and
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/// OldIdx.
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///
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void handleMoveUp(LiveInterval &LI) {
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// First look for a kill at OldIdx.
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LiveInterval::iterator I = LI.find(OldIdx.getBaseIndex());
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LiveInterval::iterator E = LI.end();
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// Is LI even live at OldIdx?
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if (I == E || SlotIndex::isEarlierInstr(OldIdx, I->start))
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return;
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// Handle a live-in value.
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if (!SlotIndex::isSameInstr(I->start, OldIdx)) {
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// If the live-in value isn't killed here, there is nothing to do.
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if (!SlotIndex::isSameInstr(OldIdx, I->end))
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return;
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// Adjust I->end to end at NewIdx. If we are hoisting a kill above
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// another use, we need to search for that use. Case 5 above.
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I->end = NewIdx.getRegSlot(I->end.isEarlyClobber());
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++I;
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// If OldIdx also defines a value, there couldn't have been another use.
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if (I == E || !SlotIndex::isSameInstr(I->start, OldIdx)) {
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// No def, search for the new kill.
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// This can never be an early clobber kill since there is no def.
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llvm::prior(I)->end = findLastUseBefore(LI.reg).getRegSlot();
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return;
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}
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}
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for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
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EI != EE; ++EI) {
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LiveInterval* LI = EI->first;
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LiveRange* LR = EI->second;
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BR[LI->reg].Def = LR;
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// Now deal with the def at OldIdx.
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assert(I != E && SlotIndex::isSameInstr(I->start, OldIdx) && "No def?");
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VNInfo *DefVNI = I->valno;
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assert(DefVNI->def == I->start && "Inconsistent def");
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DefVNI->def = NewIdx.getRegSlot(I->start.isEarlyClobber());
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// Check for an existing def at NewIdx.
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LiveInterval::iterator NewI = LI.find(NewIdx.getRegSlot());
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if (SlotIndex::isSameInstr(NewI->start, NewIdx)) {
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assert(NewI->valno != DefVNI && "Same value defined more than once?");
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// There is an existing def at NewIdx.
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if (I->end.isDead()) {
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// Case 3: Remove the dead def at OldIdx.
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LI.removeValNo(DefVNI);
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return;
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}
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// Case 4: Replace def at NewIdx with live def at OldIdx.
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I->start = DefVNI->def;
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LI.removeValNo(NewI->valno);
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||||
return;
|
||||
}
|
||||
|
||||
return BR;
|
||||
// There is no existing def at NewIdx. Hoist DefVNI.
|
||||
if (!I->end.isDead()) {
|
||||
// Leave the end point of a live def.
|
||||
I->start = DefVNI->def;
|
||||
return;
|
||||
}
|
||||
|
||||
// DefVNI is a dead def. It may have been moved across other values in LI,
|
||||
// so move I up to NewI. Slide [NewI;I) down one position.
|
||||
std::copy_backward(NewI, I, llvm::next(I));
|
||||
*NewI = LiveRange(DefVNI->def, NewIdx.getDeadSlot(), DefVNI);
|
||||
}
|
||||
|
||||
void moveKillFlags(unsigned reg, SlotIndex OldIdx, SlotIndex newKillIdx) {
|
||||
MachineInstr* OldKillMI = LIS.getInstructionFromIndex(OldIdx);
|
||||
if (!OldKillMI->killsRegister(reg))
|
||||
return; // Bail out if we don't have kill flags on the old register.
|
||||
MachineInstr* NewKillMI = LIS.getInstructionFromIndex(newKillIdx);
|
||||
assert(OldKillMI->killsRegister(reg) && "Old 'kill' instr isn't a kill.");
|
||||
assert(!NewKillMI->killsRegister(reg) &&
|
||||
"New kill instr is already a kill.");
|
||||
OldKillMI->clearRegisterKills(reg, &TRI);
|
||||
NewKillMI->addRegisterKilled(reg, &TRI);
|
||||
}
|
||||
|
||||
void updateRegMaskSlots(SlotIndex OldIdx) {
|
||||
void updateRegMaskSlots() {
|
||||
SmallVectorImpl<SlotIndex>::iterator RI =
|
||||
std::lower_bound(LIS.RegMaskSlots.begin(), LIS.RegMaskSlots.end(),
|
||||
OldIdx);
|
||||
@ -1257,7 +1251,7 @@ private:
|
||||
}
|
||||
|
||||
// Return the last use of reg between NewIdx and OldIdx.
|
||||
SlotIndex findLastUseBefore(unsigned Reg, SlotIndex OldIdx) {
|
||||
SlotIndex findLastUseBefore(unsigned Reg) {
|
||||
SlotIndex LastUse = NewIdx;
|
||||
|
||||
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
||||
@ -1291,233 +1285,25 @@ private:
|
||||
}
|
||||
return LastUse;
|
||||
}
|
||||
|
||||
void moveEnteringUpFrom(SlotIndex OldIdx, IntRangePair& P) {
|
||||
LiveInterval* LI = P.first;
|
||||
LiveRange* LR = P.second;
|
||||
bool LiveThrough = LR->end > OldIdx.getRegSlot();
|
||||
if (LiveThrough)
|
||||
return;
|
||||
SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
|
||||
if (LastUse != NewIdx)
|
||||
moveKillFlags(LI->reg, NewIdx, LastUse);
|
||||
LR->end = LastUse.getRegSlot(LR->end.isEarlyClobber());
|
||||
}
|
||||
|
||||
void moveEnteringDownFrom(SlotIndex OldIdx, IntRangePair& P) {
|
||||
LiveInterval* LI = P.first;
|
||||
LiveRange* LR = P.second;
|
||||
// Extend the LiveRange if NewIdx is past the end.
|
||||
if (NewIdx > LR->end) {
|
||||
// Move kill flags if OldIdx was not originally the end
|
||||
// (otherwise LR->end points to an invalid slot).
|
||||
if (LR->end.getRegSlot() != OldIdx.getRegSlot()) {
|
||||
assert(LR->end > OldIdx && "LiveRange does not cover original slot");
|
||||
moveKillFlags(LI->reg, LR->end, NewIdx);
|
||||
}
|
||||
LR->end = NewIdx.getRegSlot(LR->end.isEarlyClobber());
|
||||
}
|
||||
}
|
||||
|
||||
void moveAllEnteringFrom(SlotIndex OldIdx, RangeSet& Entering) {
|
||||
bool GoingUp = NewIdx < OldIdx;
|
||||
|
||||
if (GoingUp) {
|
||||
for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
|
||||
EI != EE; ++EI)
|
||||
moveEnteringUpFrom(OldIdx, *EI);
|
||||
} else {
|
||||
for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
|
||||
EI != EE; ++EI)
|
||||
moveEnteringDownFrom(OldIdx, *EI);
|
||||
}
|
||||
}
|
||||
|
||||
void moveInternalFrom(SlotIndex OldIdx, IntRangePair& P) {
|
||||
LiveInterval* LI = P.first;
|
||||
LiveRange* LR = P.second;
|
||||
assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
|
||||
LR->end <= OldIdx.getDeadSlot() &&
|
||||
"Range should be internal to OldIdx.");
|
||||
LiveRange Tmp(*LR);
|
||||
Tmp.start = NewIdx.getRegSlot(LR->start.isEarlyClobber());
|
||||
Tmp.valno->def = Tmp.start;
|
||||
Tmp.end = LR->end.isDead() ? NewIdx.getDeadSlot() : NewIdx.getRegSlot();
|
||||
LI->removeRange(*LR);
|
||||
LI->addRange(Tmp);
|
||||
}
|
||||
|
||||
void moveAllInternalFrom(SlotIndex OldIdx, RangeSet& Internal) {
|
||||
for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
|
||||
II != IE; ++II)
|
||||
moveInternalFrom(OldIdx, *II);
|
||||
}
|
||||
|
||||
void moveExitingFrom(SlotIndex OldIdx, IntRangePair& P) {
|
||||
LiveRange* LR = P.second;
|
||||
assert(OldIdx < LR->start && LR->start < OldIdx.getDeadSlot() &&
|
||||
"Range should start in OldIdx.");
|
||||
assert(LR->end > OldIdx.getDeadSlot() && "Range should exit OldIdx.");
|
||||
SlotIndex NewStart = NewIdx.getRegSlot(LR->start.isEarlyClobber());
|
||||
LR->start = NewStart;
|
||||
LR->valno->def = NewStart;
|
||||
}
|
||||
|
||||
void moveAllExitingFrom(SlotIndex OldIdx, RangeSet& Exiting) {
|
||||
for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
|
||||
EI != EE; ++EI)
|
||||
moveExitingFrom(OldIdx, *EI);
|
||||
}
|
||||
|
||||
void moveEnteringUpFromInto(SlotIndex OldIdx, IntRangePair& P,
|
||||
BundleRanges& BR) {
|
||||
LiveInterval* LI = P.first;
|
||||
LiveRange* LR = P.second;
|
||||
bool LiveThrough = LR->end > OldIdx.getRegSlot();
|
||||
if (LiveThrough) {
|
||||
assert((LR->start < NewIdx || BR[LI->reg].Def == LR) &&
|
||||
"Def in bundle should be def range.");
|
||||
assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
|
||||
"If bundle has use for this reg it should be LR.");
|
||||
BR[LI->reg].Use = LR;
|
||||
return;
|
||||
}
|
||||
|
||||
SlotIndex LastUse = findLastUseBefore(LI->reg, OldIdx);
|
||||
moveKillFlags(LI->reg, OldIdx, LastUse);
|
||||
|
||||
if (LR->start < NewIdx) {
|
||||
// Becoming a new entering range.
|
||||
assert(BR[LI->reg].Dead == 0 && BR[LI->reg].Def == 0 &&
|
||||
"Bundle shouldn't be re-defining reg mid-range.");
|
||||
assert((BR[LI->reg].Use == 0 || BR[LI->reg].Use == LR) &&
|
||||
"Bundle shouldn't have different use range for same reg.");
|
||||
LR->end = LastUse.getRegSlot();
|
||||
BR[LI->reg].Use = LR;
|
||||
} else {
|
||||
// Becoming a new Dead-def.
|
||||
assert(LR->start == NewIdx.getRegSlot(LR->start.isEarlyClobber()) &&
|
||||
"Live range starting at unexpected slot.");
|
||||
assert(BR[LI->reg].Def == LR && "Reg should have def range.");
|
||||
assert(BR[LI->reg].Dead == 0 &&
|
||||
"Can't have def and dead def of same reg in a bundle.");
|
||||
LR->end = LastUse.getDeadSlot();
|
||||
BR[LI->reg].Dead = BR[LI->reg].Def;
|
||||
BR[LI->reg].Def = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void moveEnteringDownFromInto(SlotIndex OldIdx, IntRangePair& P,
|
||||
BundleRanges& BR) {
|
||||
LiveInterval* LI = P.first;
|
||||
LiveRange* LR = P.second;
|
||||
if (NewIdx > LR->end) {
|
||||
// Range extended to bundle. Add to bundle uses.
|
||||
// Note: Currently adds kill flags to bundle start.
|
||||
assert(BR[LI->reg].Use == 0 &&
|
||||
"Bundle already has use range for reg.");
|
||||
moveKillFlags(LI->reg, LR->end, NewIdx);
|
||||
LR->end = NewIdx.getRegSlot();
|
||||
BR[LI->reg].Use = LR;
|
||||
} else {
|
||||
assert(BR[LI->reg].Use != 0 &&
|
||||
"Bundle should already have a use range for reg.");
|
||||
}
|
||||
}
|
||||
|
||||
void moveAllEnteringFromInto(SlotIndex OldIdx, RangeSet& Entering,
|
||||
BundleRanges& BR) {
|
||||
bool GoingUp = NewIdx < OldIdx;
|
||||
|
||||
if (GoingUp) {
|
||||
for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
|
||||
EI != EE; ++EI)
|
||||
moveEnteringUpFromInto(OldIdx, *EI, BR);
|
||||
} else {
|
||||
for (RangeSet::iterator EI = Entering.begin(), EE = Entering.end();
|
||||
EI != EE; ++EI)
|
||||
moveEnteringDownFromInto(OldIdx, *EI, BR);
|
||||
}
|
||||
}
|
||||
|
||||
void moveInternalFromInto(SlotIndex OldIdx, IntRangePair& P,
|
||||
BundleRanges& BR) {
|
||||
// TODO: Sane rules for moving ranges into bundles.
|
||||
}
|
||||
|
||||
void moveAllInternalFromInto(SlotIndex OldIdx, RangeSet& Internal,
|
||||
BundleRanges& BR) {
|
||||
for (RangeSet::iterator II = Internal.begin(), IE = Internal.end();
|
||||
II != IE; ++II)
|
||||
moveInternalFromInto(OldIdx, *II, BR);
|
||||
}
|
||||
|
||||
void moveExitingFromInto(SlotIndex OldIdx, IntRangePair& P,
|
||||
BundleRanges& BR) {
|
||||
LiveInterval* LI = P.first;
|
||||
LiveRange* LR = P.second;
|
||||
|
||||
assert(LR->start.isRegister() &&
|
||||
"Don't know how to merge exiting ECs into bundles yet.");
|
||||
|
||||
if (LR->end > NewIdx.getDeadSlot()) {
|
||||
// This range is becoming an exiting range on the bundle.
|
||||
// If there was an old dead-def of this reg, delete it.
|
||||
if (BR[LI->reg].Dead != 0) {
|
||||
LI->removeRange(*BR[LI->reg].Dead);
|
||||
BR[LI->reg].Dead = 0;
|
||||
}
|
||||
assert(BR[LI->reg].Def == 0 &&
|
||||
"Can't have two defs for the same variable exiting a bundle.");
|
||||
LR->start = NewIdx.getRegSlot();
|
||||
LR->valno->def = LR->start;
|
||||
BR[LI->reg].Def = LR;
|
||||
} else {
|
||||
// This range is becoming internal to the bundle.
|
||||
assert(LR->end == NewIdx.getRegSlot() &&
|
||||
"Can't bundle def whose kill is before the bundle");
|
||||
if (BR[LI->reg].Dead || BR[LI->reg].Def) {
|
||||
// Already have a def for this. Just delete range.
|
||||
LI->removeRange(*LR);
|
||||
} else {
|
||||
// Make range dead, record.
|
||||
LR->end = NewIdx.getDeadSlot();
|
||||
BR[LI->reg].Dead = LR;
|
||||
assert(BR[LI->reg].Use == LR &&
|
||||
"Range becoming dead should currently be use.");
|
||||
}
|
||||
// In both cases the range is no longer a use on the bundle.
|
||||
BR[LI->reg].Use = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void moveAllExitingFromInto(SlotIndex OldIdx, RangeSet& Exiting,
|
||||
BundleRanges& BR) {
|
||||
for (RangeSet::iterator EI = Exiting.begin(), EE = Exiting.end();
|
||||
EI != EE; ++EI)
|
||||
moveExitingFromInto(OldIdx, *EI, BR);
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
void LiveIntervals::handleMove(MachineInstr* MI) {
|
||||
assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
|
||||
SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
|
||||
Indexes->removeMachineInstrFromMaps(MI);
|
||||
SlotIndex NewIndex = MI->isInsideBundle() ?
|
||||
Indexes->getInstructionIndex(MI) :
|
||||
Indexes->insertMachineInstrInMaps(MI);
|
||||
SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);
|
||||
assert(getMBBStartIdx(MI->getParent()) <= OldIndex &&
|
||||
OldIndex < getMBBEndIdx(MI->getParent()) &&
|
||||
"Cannot handle moves across basic block boundaries.");
|
||||
assert(!MI->isBundled() && "Can't handle bundled instructions yet.");
|
||||
|
||||
HMEditor HME(*this, *MRI, *TRI, NewIndex);
|
||||
HME.moveAllRangesFrom(MI, OldIndex);
|
||||
HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex);
|
||||
HME.updateAllRanges(MI);
|
||||
}
|
||||
|
||||
void LiveIntervals::handleMoveIntoBundle(MachineInstr* MI,
|
||||
MachineInstr* BundleStart) {
|
||||
SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
|
||||
SlotIndex NewIndex = Indexes->getInstructionIndex(BundleStart);
|
||||
HMEditor HME(*this, *MRI, *TRI, NewIndex);
|
||||
HME.moveAllRangesInto(MI, BundleStart);
|
||||
HMEditor HME(*this, *MRI, *TRI, OldIndex, NewIndex);
|
||||
HME.updateAllRanges(MI);
|
||||
}
|
||||
|
||||
73
test/CodeGen/X86/handle-move.ll
Normal file
73
test/CodeGen/X86/handle-move.ll
Normal file
@ -0,0 +1,73 @@
|
||||
; RUN: llc -march=x86-64 -mcpu=core2 -fast-isel -enable-misched -misched=shuffle -misched-bottomup -verify-machineinstrs < %s
|
||||
; RUN: llc -march=x86-64 -mcpu=core2 -fast-isel -enable-misched -misched=shuffle -misched-topdown -verify-machineinstrs < %s
|
||||
;
|
||||
; Test the LiveIntervals::handleMove() function.
|
||||
;
|
||||
; Moving the DIV32r instruction exercises the regunit update code because
|
||||
; %EDX has a live range into the function and is used by the DIV32r.
|
||||
;
|
||||
; Here sinking a kill + dead def:
|
||||
; 144B -> 180B: DIV32r %vreg4, %EAX<imp-def>, %EDX<imp-def,dead>, %EFLAGS<imp-def,dead>, %EAX<imp-use,kill>, %EDX<imp-use>
|
||||
; %vreg4: [48r,144r:0) 0@48r
|
||||
; --> [48r,180r:0) 0@48r
|
||||
; DH: [0B,16r:0)[128r,144r:2)[144r,144d:1) 0@0B-phi 1@144r 2@128r
|
||||
; --> [0B,16r:0)[128r,180r:2)[180r,180d:1) 0@0B-phi 1@180r 2@128r
|
||||
; DL: [0B,16r:0)[128r,144r:2)[144r,144d:1) 0@0B-phi 1@144r 2@128r
|
||||
; --> [0B,16r:0)[128r,180r:2)[180r,180d:1) 0@0B-phi 1@180r 2@128r
|
||||
;
|
||||
define i32 @f1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind uwtable readnone ssp {
|
||||
entry:
|
||||
%y = add i32 %c, 1
|
||||
%x = udiv i32 %b, %a
|
||||
%add = add nsw i32 %y, %x
|
||||
ret i32 %add
|
||||
}
|
||||
|
||||
; Same as above, but moving a kill + live def:
|
||||
; 144B -> 180B: DIV32r %vreg4, %EAX<imp-def,dead>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-use,kill>, %EDX<imp-use>
|
||||
; %vreg4: [48r,144r:0) 0@48r
|
||||
; --> [48r,180r:0) 0@48r
|
||||
; DH: [0B,16r:0)[128r,144r:2)[144r,184r:1) 0@0B-phi 1@144r 2@128r
|
||||
; --> [0B,16r:0)[128r,180r:2)[180r,184r:1) 0@0B-phi 1@180r 2@128r
|
||||
; DL: [0B,16r:0)[128r,144r:2)[144r,184r:1) 0@0B-phi 1@144r 2@128r
|
||||
; --> [0B,16r:0)[128r,180r:2)[180r,184r:1) 0@0B-phi 1@180r 2@128r
|
||||
;
|
||||
define i32 @f2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind uwtable readnone ssp {
|
||||
entry:
|
||||
%y = sub i32 %c, %d
|
||||
%x = urem i32 %b, %a
|
||||
%add = add nsw i32 %x, %y
|
||||
ret i32 %add
|
||||
}
|
||||
|
||||
; Moving a use below the existing kill (%vreg5):
|
||||
; Moving a tied virtual register def (%vreg11):
|
||||
;
|
||||
; 96B -> 120B: %vreg11<def,tied1> = SUB32rr %vreg11<tied0>, %vreg5
|
||||
; %vreg11: [80r,96r:1)[96r,144r:0) 0@96r 1@80r
|
||||
; --> [80r,120r:1)[120r,144r:0) 0@120r 1@80r
|
||||
; %vreg5: [16r,112r:0) 0@16r
|
||||
; --> [16r,120r:0) 0@16r
|
||||
;
|
||||
define i32 @f3(i32 %a, i32 %b, i32 %c, i32 %d) nounwind uwtable readnone ssp {
|
||||
entry:
|
||||
%y = sub i32 %a, %b
|
||||
%x = add i32 %a, %b
|
||||
%r = mul i32 %x, %y
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
; Move EFLAGS dead def across another def:
|
||||
; handleMove 208B -> 36B: %EDX<def> = MOV32r0 %EFLAGS<imp-def,dead>
|
||||
; EFLAGS: [20r,20d:4)[160r,160d:3)[208r,208d:0)[224r,224d:1)[272r,272d:2)[304r,304d:5) 0@208r 1@224r 2@272r 3@160r 4@20r 5@304r
|
||||
; --> [20r,20d:4)[36r,36d:0)[160r,160d:3)[224r,224d:1)[272r,272d:2)[304r,304d:5) 0@36r 1@224r 2@272r 3@160r 4@20r 5@304r
|
||||
;
|
||||
define i32 @f4(i32 %a, i32 %b, i32 %c, i32 %d) nounwind uwtable readnone ssp {
|
||||
entry:
|
||||
%x = sub i32 %a, %b
|
||||
%y = sub i32 %b, %c
|
||||
%z = sub i32 %c, %d
|
||||
%r1 = udiv i32 %x, %y
|
||||
%r2 = mul i32 %z, %r1
|
||||
ret i32 %r2
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user