MIR Serialization: Serialize the virtual register definitions.

The virtual registers are serialized using a YAML sequence of YAML inline
mappings. Each mapping has the id of the virtual register and the register
class.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10981


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241868 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alex Lorenz
2015-07-09 22:23:13 +00:00
parent 81e7e2dfab
commit ad6702ec23
5 changed files with 141 additions and 7 deletions

View File

@@ -49,6 +49,8 @@ class MIRParserImpl {
LLVMContext &Context;
StringMap<std::unique_ptr<yaml::MachineFunction>> Functions;
SlotMapping IRSlots;
/// Maps from register class names to register classes.
StringMap<const TargetRegisterClass *> Names2RegClasses;
public:
MIRParserImpl(std::unique_ptr<MemoryBuffer> Contents, StringRef Filename,
@@ -100,7 +102,8 @@ public:
const yaml::MachineBasicBlock &YamlMBB,
const PerFunctionMIParsingState &PFS);
bool initializeRegisterInfo(MachineRegisterInfo &RegInfo,
bool initializeRegisterInfo(const MachineFunction &MF,
MachineRegisterInfo &RegInfo,
const yaml::MachineFunction &YamlMF);
bool initializeFrameInfo(MachineFrameInfo &MFI,
@@ -117,6 +120,14 @@ private:
/// Create an empty function with the given name.
void createDummyFunction(StringRef Name, Module &M);
void initNames2RegClasses(const MachineFunction &MF);
/// Check if the given identifier is a name of a register class.
///
/// Return null if the name isn't a register class.
const TargetRegisterClass *getRegClass(const MachineFunction &MF,
StringRef Name);
};
} // end namespace llvm
@@ -247,7 +258,7 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
MF.setAlignment(YamlMF.Alignment);
MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
MF.setHasInlineAsm(YamlMF.HasInlineAsm);
if (initializeRegisterInfo(MF.getRegInfo(), YamlMF))
if (initializeRegisterInfo(MF, MF.getRegInfo(), YamlMF))
return true;
if (initializeFrameInfo(*MF.getFrameInfo(), YamlMF.FrameInfo))
return true;
@@ -318,7 +329,8 @@ bool MIRParserImpl::initializeMachineBasicBlock(
}
bool MIRParserImpl::initializeRegisterInfo(
MachineRegisterInfo &RegInfo, const yaml::MachineFunction &YamlMF) {
const MachineFunction &MF, MachineRegisterInfo &RegInfo,
const yaml::MachineFunction &YamlMF) {
assert(RegInfo.isSSA());
if (!YamlMF.IsSSA)
RegInfo.leaveSSA();
@@ -326,6 +338,18 @@ bool MIRParserImpl::initializeRegisterInfo(
if (!YamlMF.TracksRegLiveness)
RegInfo.invalidateLiveness();
RegInfo.enableSubRegLiveness(YamlMF.TracksSubRegLiveness);
// Parse the virtual register information.
for (const auto &VReg : YamlMF.VirtualRegisters) {
const auto *RC = getRegClass(MF, VReg.Class.Value);
if (!RC)
return error(VReg.Class.SourceRange.Start,
Twine("use of undefined register class '") +
VReg.Class.Value + "'");
// TODO: create the mapping from IDs to registers so that the virtual
// register references can be parsed correctly.
RegInfo.createVirtualRegister(RC);
}
return false;
}
@@ -395,6 +419,26 @@ SMDiagnostic MIRParserImpl::diagFromLLVMAssemblyDiag(const SMDiagnostic &Error,
Error.getFixIts());
}
void MIRParserImpl::initNames2RegClasses(const MachineFunction &MF) {
if (!Names2RegClasses.empty())
return;
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; ++I) {
const auto *RC = TRI->getRegClass(I);
Names2RegClasses.insert(
std::make_pair(StringRef(TRI->getRegClassName(RC)).lower(), RC));
}
}
const TargetRegisterClass *MIRParserImpl::getRegClass(const MachineFunction &MF,
StringRef Name) {
initNames2RegClasses(MF);
auto RegClassInfo = Names2RegClasses.find(Name);
if (RegClassInfo == Names2RegClasses.end())
return nullptr;
return RegClassInfo->getValue();
}
MIRParser::MIRParser(std::unique_ptr<MIRParserImpl> Impl)
: Impl(std::move(Impl)) {}