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MIR Serialization: Serialize the virtual register definitions.
The virtual registers are serialized using a YAML sequence of YAML inline mappings. Each mapping has the id of the virtual register and the register class. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10981 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241868 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -49,6 +49,8 @@ class MIRParserImpl {
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LLVMContext &Context;
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StringMap<std::unique_ptr<yaml::MachineFunction>> Functions;
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SlotMapping IRSlots;
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/// Maps from register class names to register classes.
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StringMap<const TargetRegisterClass *> Names2RegClasses;
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public:
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MIRParserImpl(std::unique_ptr<MemoryBuffer> Contents, StringRef Filename,
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@@ -100,7 +102,8 @@ public:
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const yaml::MachineBasicBlock &YamlMBB,
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const PerFunctionMIParsingState &PFS);
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bool initializeRegisterInfo(MachineRegisterInfo &RegInfo,
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bool initializeRegisterInfo(const MachineFunction &MF,
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MachineRegisterInfo &RegInfo,
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const yaml::MachineFunction &YamlMF);
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bool initializeFrameInfo(MachineFrameInfo &MFI,
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@@ -117,6 +120,14 @@ private:
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/// Create an empty function with the given name.
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void createDummyFunction(StringRef Name, Module &M);
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void initNames2RegClasses(const MachineFunction &MF);
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/// Check if the given identifier is a name of a register class.
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///
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/// Return null if the name isn't a register class.
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const TargetRegisterClass *getRegClass(const MachineFunction &MF,
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StringRef Name);
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};
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} // end namespace llvm
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@@ -247,7 +258,7 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
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MF.setAlignment(YamlMF.Alignment);
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MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
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MF.setHasInlineAsm(YamlMF.HasInlineAsm);
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if (initializeRegisterInfo(MF.getRegInfo(), YamlMF))
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if (initializeRegisterInfo(MF, MF.getRegInfo(), YamlMF))
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return true;
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if (initializeFrameInfo(*MF.getFrameInfo(), YamlMF.FrameInfo))
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return true;
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@@ -318,7 +329,8 @@ bool MIRParserImpl::initializeMachineBasicBlock(
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}
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bool MIRParserImpl::initializeRegisterInfo(
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MachineRegisterInfo &RegInfo, const yaml::MachineFunction &YamlMF) {
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const MachineFunction &MF, MachineRegisterInfo &RegInfo,
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const yaml::MachineFunction &YamlMF) {
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assert(RegInfo.isSSA());
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if (!YamlMF.IsSSA)
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RegInfo.leaveSSA();
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@@ -326,6 +338,18 @@ bool MIRParserImpl::initializeRegisterInfo(
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if (!YamlMF.TracksRegLiveness)
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RegInfo.invalidateLiveness();
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RegInfo.enableSubRegLiveness(YamlMF.TracksSubRegLiveness);
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// Parse the virtual register information.
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for (const auto &VReg : YamlMF.VirtualRegisters) {
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const auto *RC = getRegClass(MF, VReg.Class.Value);
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if (!RC)
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return error(VReg.Class.SourceRange.Start,
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Twine("use of undefined register class '") +
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VReg.Class.Value + "'");
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// TODO: create the mapping from IDs to registers so that the virtual
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// register references can be parsed correctly.
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RegInfo.createVirtualRegister(RC);
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}
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return false;
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}
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@@ -395,6 +419,26 @@ SMDiagnostic MIRParserImpl::diagFromLLVMAssemblyDiag(const SMDiagnostic &Error,
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Error.getFixIts());
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}
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void MIRParserImpl::initNames2RegClasses(const MachineFunction &MF) {
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if (!Names2RegClasses.empty())
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return;
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; ++I) {
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const auto *RC = TRI->getRegClass(I);
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Names2RegClasses.insert(
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std::make_pair(StringRef(TRI->getRegClassName(RC)).lower(), RC));
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}
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}
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const TargetRegisterClass *MIRParserImpl::getRegClass(const MachineFunction &MF,
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StringRef Name) {
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initNames2RegClasses(MF);
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auto RegClassInfo = Names2RegClasses.find(Name);
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if (RegClassInfo == Names2RegClasses.end())
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return nullptr;
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return RegClassInfo->getValue();
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}
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MIRParser::MIRParser(std::unique_ptr<MIRParserImpl> Impl)
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: Impl(std::move(Impl)) {}
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