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Use the auto-generated call matcher. Remove a broken impl of the frameaddr/returnaddr

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intrinsics.

Autogen frameindex matcher


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26107 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-02-10 07:35:42 +00:00
parent f613fcb741
commit ad7a3e6208
3 changed files with 34 additions and 61 deletions
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14
lib/Target/Sparc/SparcAsmPrinter.cpp
View File

@ -57,7 +57,8 @@ namespace {
}
void printOperand(const MachineInstr *MI, int opNum);
void printMemOperand(const MachineInstr *MI, int opNum);
void printMemOperand(const MachineInstr *MI, int opNum,
const char *Modifier = 0);
void printCCOperand(const MachineInstr *MI, int opNum);
bool printInstruction(const MachineInstr *MI); // autogenerated.
@ -189,8 +190,17 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
if (CloseParen) O << ")";
}
void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) {
void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
const char *Modifier) {
printOperand(MI, opNum);
// If this is an ADD operand, emit it like normal operands.
if (Modifier && !strcmp(Modifier, "arith")) {
O << ", ";
printOperand(MI, opNum+1);
return;
}
MachineOperand::MachineOperandType OpTy = MI->getOperand(opNum+1).getType();
if ((OpTy == MachineOperand::MO_VirtualRegister ||

67
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -111,9 +111,6 @@ namespace {
unsigned CC,
bool isTailCall, SDOperand Callee, ArgListTy &Args,
SelectionDAG &DAG);
virtual std::pair<SDOperand, SDOperand>
LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
SelectionDAG &DAG);
virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
MachineBasicBlock *MBB);
@ -595,8 +592,11 @@ SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
// If the callee is a GlobalAddress node (quite common, every direct call is)
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
// Likewise ExternalSymbol -> TargetExternalSymbol.
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
std::vector<MVT::ValueType> NodeTys;
NodeTys.push_back(MVT::Other); // Returns a chain
@ -653,13 +653,6 @@ SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
return std::make_pair(RetVal, Chain);
}
std::pair<SDOperand, SDOperand> SparcTargetLowering::
LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
SelectionDAG &DAG) {
assert(0 && "Unimp");
abort();
}
// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
@ -974,6 +967,9 @@ bool SparcDAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
Offset = CurDAG->getTargetConstant(0, MVT::i32);
return true;
}
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress)
return false; // direct calls.
if (Addr.getOpcode() == ISD::ADD) {
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
@ -1007,7 +1003,11 @@ bool SparcDAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
SDOperand &R2) {
if (Addr.getOpcode() == ISD::FrameIndex) return false;
if (Addr.getOpcode() == ISD::FrameIndex) return false;
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress)
return false; // direct calls.
if (Addr.getOpcode() == ISD::ADD) {
if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
Predicate_simm13(Addr.getOperand(1).Val))
@ -1042,21 +1042,6 @@ void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
switch (N->getOpcode()) {
default: break;
case ISD::FrameIndex: {
int FI = cast<FrameIndexSDNode>(N)->getIndex();
if (N->hasOneUse()) {
Result = CurDAG->SelectNodeTo(N, SP::ADDri, MVT::i32,
CurDAG->getTargetFrameIndex(FI, MVT::i32),
CurDAG->getTargetConstant(0, MVT::i32));
return;
}
Result = CodeGenMap[Op] =
SDOperand(CurDAG->getTargetNode(SP::ADDri, MVT::i32,
CurDAG->getTargetFrameIndex(FI, MVT::i32),
CurDAG->getTargetConstant(0, MVT::i32)), 0);
return;
}
case ISD::ADD_PARTS: {
SDOperand LHSL, LHSH, RHSL, RHSH;
Select(LHSL, N->getOperand(0));
@ -1123,39 +1108,11 @@ void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
Select(MulRHS, N->getOperand(1));
unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
MulLHS, MulRHS);
MulLHS, MulRHS);
// The high part is in the Y register.
Result = CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
return;
}
case SPISD::CALL:
// FIXME: This is a workaround for a bug in tblgen.
{ // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag)
// Emits: (CALL:void (tglobaladdr:i32):$dst)
// Pattern complexity = 2 cost = 1
SDOperand N1 = N->getOperand(1);
if (N1.getOpcode() != ISD::TargetGlobalAddress &&
N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail;
SDOperand InFlag = SDOperand(0, 0);
SDOperand Chain = N->getOperand(0);
SDOperand Tmp0 = N1;
Select(Chain, Chain);
SDNode *ResNode;
if (N->getNumOperands() == 3) {
Select(InFlag, N->getOperand(2));
ResNode = CurDAG->getTargetNode(SP::CALL, MVT::Other, MVT::Flag, Tmp0,
Chain, InFlag);
} else {
ResNode = CurDAG->getTargetNode(SP::CALL, MVT::Other, MVT::Flag, Tmp0,
Chain);
}
Chain = CodeGenMap[SDOperand(N, 0)] = SDOperand(ResNode, 0);
CodeGenMap[SDOperand(N, 1)] = SDOperand(ResNode, 1);
Result = SDOperand(ResNode, Op.ResNo);
return;
}
P47Fail:;
}
SelectCode(Result, Op);

14
lib/Target/Sparc/SparcInstrInfo.td
View File

@ -68,7 +68,7 @@ def SETHIimm : PatLeaf<(imm), [{
// Addressing modes.
def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>;
def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex]>;
// Address operands
def MEMrr : Operand<i32> {
@ -444,6 +444,13 @@ def ADDri : F3_2<2, 0b000000,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
"add $b, $c, $dst",
[(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
// "LEA" forms of add (patterns to make tblgen happy)
def LEA_ADDri : F3_2<2, 0b000000,
(ops IntRegs:$dst, MEMri:$addr),
"add ${addr:arith}, $dst",
[(set IntRegs:$dst, ADDRri:$addr)]>;
def ADDCCrr : F3_1<2, 0b010000,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"addcc $b, $c, $dst", []>;
@ -871,12 +878,11 @@ def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)),
def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)),
(ADDri IntRegs:$r, tconstpool:$in)>;
// Calls:
def : Pat<(call tglobaladdr:$dst),
(CALL tglobaladdr:$dst)>;
def : Pat<(call externalsym:$dst),
(CALL externalsym:$dst)>;
def : Pat<(call texternalsym:$dst),
(CALL texternalsym:$dst)>;
def : Pat<(ret), (RETL)>;