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Fix incorrect check for sign-extended constant BUILD_VECTOR.

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<rdar://problem/10298332>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142371 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2011-10-18 17:34:51 +00:00
parent db2b18feba
commit ad952ad8f0
2 changed files with 12 additions and 1 deletions
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2
lib/Target/ARM/ARMISelLowering.cpp
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@ -4527,7 +4527,7 @@ static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
unsigned HalfSize = EltSize / 2;
if (isSigned) {
int64_t SExtVal = C->getSExtValue();
if ((SExtVal >> HalfSize) != (SExtVal >> EltSize))
if (SExtVal != SExtVal << (64 - HalfSize) >> (64 - HalfSize))
return false;
} else {
if ((C->getZExtValue() >> HalfSize) != 0)

11
test/CodeGen/ARM/vmul.ll
View File

@ -514,3 +514,14 @@ entry:
store <8 x i8> %10, <8 x i8>* %11, align 8
ret void
}
; If one operand has a zero-extend and the other a sign-extend, vmull
; cannot be used.
define i16 @vmullWithInconsistentExtensions(<8 x i8> %vec) {
; CHECK: vmullWithInconsistentExtensions
; CHECK-NOT: vmull.s8
%1 = sext <8 x i8> %vec to <8 x i16>
%2 = mul <8 x i16> %1, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
%3 = extractelement <8 x i16> %2, i32 0
ret i16 %3
}