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Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91381 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -5750,6 +5750,15 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
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return SDValue();
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SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
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// Use sbb x, x to materialize carry bit into a GPR.
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if (X86CC == X86::COND_B) {
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return DAG.getNode(ISD::AND, dl, MVT::i8,
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DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
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DAG.getConstant(X86CC, MVT::i8), Cond),
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DAG.getConstant(1, MVT::i8));
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}
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return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
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DAG.getConstant(X86CC, MVT::i8), Cond);
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}
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@ -5902,9 +5911,18 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
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Cond = NewCond;
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}
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// Look pass (and (setcc_carry (cmp ...)), 1).
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if (Cond.getOpcode() == ISD::AND &&
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Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
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ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
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if (C && C->getAPIntValue() == 1)
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Cond = Cond.getOperand(0);
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}
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// If condition flag is set by a X86ISD::CMP, then use it as the condition
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// setting operand in place of the X86ISD::SETCC.
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if (Cond.getOpcode() == X86ISD::SETCC) {
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if (Cond.getOpcode() == X86ISD::SETCC ||
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Cond.getOpcode() == X86ISD::SETCC_CARRY) {
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CC = Cond.getOperand(0);
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SDValue Cmp = Cond.getOperand(1);
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@ -5987,9 +6005,18 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
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Cond = LowerXALUO(Cond, DAG);
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#endif
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// Look pass (and (setcc_carry (cmp ...)), 1).
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if (Cond.getOpcode() == ISD::AND &&
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Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
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ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
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if (C && C->getAPIntValue() == 1)
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Cond = Cond.getOperand(0);
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}
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// If condition flag is set by a X86ISD::CMP, then use it as the condition
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// setting operand in place of the X86ISD::SETCC.
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if (Cond.getOpcode() == X86ISD::SETCC) {
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if (Cond.getOpcode() == X86ISD::SETCC ||
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Cond.getOpcode() == X86ISD::SETCC_CARRY) {
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CC = Cond.getOperand(0);
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SDValue Cmp = Cond.getOperand(1);
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@ -7376,6 +7403,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::COMI: return "X86ISD::COMI";
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case X86ISD::UCOMI: return "X86ISD::UCOMI";
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case X86ISD::SETCC: return "X86ISD::SETCC";
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case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
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case X86ISD::CMOV: return "X86ISD::CMOV";
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case X86ISD::BRCOND: return "X86ISD::BRCOND";
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case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
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@ -8950,11 +8978,42 @@ static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
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EVT VT = N0.getValueType();
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// fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
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// since the result of setcc_c is all zero's or all ones.
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if (N1C && N0.getOpcode() == ISD::AND &&
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N0.getOperand(1).getOpcode() == ISD::Constant) {
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SDValue N00 = N0.getOperand(0);
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if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
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((N00.getOpcode() == ISD::ANY_EXTEND ||
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N00.getOpcode() == ISD::ZERO_EXTEND) &&
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N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
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APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
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APInt ShAmt = N1C->getAPIntValue();
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Mask = Mask.shl(ShAmt);
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if (Mask != 0)
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return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
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N00, DAG.getConstant(Mask, VT));
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}
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}
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return SDValue();
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}
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/// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
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/// when possible.
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static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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EVT VT = N->getValueType(0);
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if (!VT.isVector() && VT.isInteger() &&
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N->getOpcode() == ISD::SHL)
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return PerformSHLCombine(N, DAG);
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// On X86 with SSE2 support, we can transform this to a vector shift if
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// all elements are shifted by the same amount. We can't do this in legalize
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// because the a constant vector is typically transformed to a constant pool
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@ -8962,7 +9021,6 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
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if (!Subtarget->hasSSE2())
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return SDValue();
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EVT VT = N->getValueType(0);
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if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
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return SDValue();
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@ -118,6 +118,10 @@ namespace llvm {
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/// operand produced by a CMP instruction.
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SETCC,
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// Same as SETCC except it's materialized with a sbb and the value is all
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// one's or all zero's.
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SETCC_CARRY,
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/// X86 conditional moves. Operand 0 and operand 1 are the two values
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/// to select from. Operand 2 is the condition code, and operand 3 is the
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/// flag operand produced by a CMP or TEST instruction. It also writes a
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@ -1333,6 +1333,15 @@ def CMOVNO64rm : RI<0x41, MRMSrcMem, // if !overflow, GR64 = [mem64]
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X86_COND_NO, EFLAGS))]>, TB;
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} // isTwoAddress
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// Use sbb to materialize carry flag into a GPR.
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let Defs = [EFLAGS], Uses = [EFLAGS], isCodeGenOnly = 1 in
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def SETB_C64r : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins),
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"sbb{q}\t$dst, $dst",
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[(set GR64:$dst, (zext (X86setcc_c X86_COND_B, EFLAGS)))]>;
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def : Pat<(i64 (anyext (X86setcc_c X86_COND_B, EFLAGS))),
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(SETB_C64r)>;
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//===----------------------------------------------------------------------===//
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// Conversion Instructions...
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//
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@ -87,6 +87,7 @@ def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
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def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond,
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[SDNPHasChain]>;
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def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>;
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def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC>;
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def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas,
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[SDNPHasChain, SDNPInFlag, SDNPOutFlag, SDNPMayStore,
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@ -3059,6 +3060,21 @@ let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in
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def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>; // AH = flags
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let Uses = [EFLAGS] in {
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// Use sbb to materialize carry bit.
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let Defs = [EFLAGS], isCodeGenOnly = 1 in {
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def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins),
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"sbb{b}\t$dst, $dst",
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[(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
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def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins),
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"sbb{w}\t$dst, $dst",
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[(set GR16:$dst, (zext (X86setcc_c X86_COND_B, EFLAGS)))]>,
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OpSize;
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def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins),
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"sbb{l}\t$dst, $dst",
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[(set GR32:$dst, (zext (X86setcc_c X86_COND_B, EFLAGS)))]>;
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} // isCodeGenOnly
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def SETEr : I<0x94, MRM0r,
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(outs GR8 :$dst), (ins),
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"sete\t$dst",
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@ -4169,6 +4185,12 @@ def : Pat<(store (shld (loadi16 addr:$dst), (i8 imm:$amt1),
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GR16:$src2, (i8 imm:$amt2)), addr:$dst),
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(SHLD16mri8 addr:$dst, GR16:$src2, (i8 imm:$amt1))>;
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// (anyext (setcc_carry)) -> (zext (setcc_carry))
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def : Pat<(i16 (anyext (X86setcc_c X86_COND_B, EFLAGS))),
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(SETB_C16r)>;
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def : Pat<(i32 (anyext (X86setcc_c X86_COND_B, EFLAGS))),
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(SETB_C32r)>;
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//===----------------------------------------------------------------------===//
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// EFLAGS-defining Patterns
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//===----------------------------------------------------------------------===//
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@ -1,4 +1,8 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
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; rdar://7329206
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; Use sbb x, x to materialize carry bit in a GPR. The value is either
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; all 1's or all 0's.
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define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
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entry:
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@ -11,3 +15,22 @@ entry:
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ret i16 %iftmp.1.0
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}
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define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp {
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entry:
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; CHECK: t2:
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; CHECK: sbbl %eax, %eax
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; CHECK: andl $32, %eax
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%0 = icmp ult i16 %x, 26 ; <i1> [#uses=1]
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%iftmp.0.0 = select i1 %0, i16 32, i16 0 ; <i16> [#uses=1]
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ret i16 %iftmp.0.0
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}
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define i64 @t3(i64 %x) nounwind readnone ssp {
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entry:
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; CHECK: t3:
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; CHECK: sbbq %rax, %rax
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; CHECK: andq $64, %rax
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%0 = icmp ult i64 %x, 18 ; <i1> [#uses=1]
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%iftmp.2.0 = select i1 %0, i64 64, i64 0 ; <i64> [#uses=1]
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ret i64 %iftmp.2.0
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}
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