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Factor a little more code into EmitCmp, which should have been done in the first

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place.  No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143078 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
2011-10-26 23:25:44 +00:00
parent 75698f346f
commit ade620065d
1 changed files with 16 additions and 23 deletions
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39
lib/Target/ARM/ARMFastISel.cpp
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@@ -173,7 +173,7 @@ class ARMFastISel : public FastISel {
private: private:
bool isTypeLegal(Type *Ty, MVT &VT); bool isTypeLegal(Type *Ty, MVT &VT);
bool isLoadTypeLegal(Type *Ty, MVT &VT); bool isLoadTypeLegal(Type *Ty, MVT &VT);
bool ARMEmitCmp(Type *Ty, const Value *Src1Value, const Value *Src2Value); bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value);
bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr); bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr);
bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr); bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr);
bool ARMComputeAddress(const Value *Obj, Address &Addr); bool ARMComputeAddress(const Value *Obj, Address &Addr);
@@ -1117,16 +1117,9 @@ bool ARMFastISel::SelectBranch(const Instruction *I) {
if (ARMPred == ARMCC::AL) return false; if (ARMPred == ARMCC::AL) return false;
// Emit the compare. // Emit the compare.
Type *Ty = CI->getOperand(0)->getType(); if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1)))
if (!ARMEmitCmp(Ty, CI->getOperand(0), CI->getOperand(1)))
return false; return false;
// For floating point we need to move the result to a comparison register
// that we can then use for branches.
if (Ty->isFloatTy() || Ty->isDoubleTy())
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(ARM::FMSTAT)));
unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc; unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc)) BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
.addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR); .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
@@ -1188,13 +1181,14 @@ bool ARMFastISel::SelectBranch(const Instruction *I) {
return true; return true;
} }
bool ARMFastISel::ARMEmitCmp(Type *Ty, const Value *Src1Value, bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value) {
const Value *Src2Value) {
MVT VT; MVT VT;
Type *Ty = Src1Value->getType();
if (!isTypeLegal(Ty, VT)) if (!isTypeLegal(Ty, VT))
return false; return false;
if ((Ty->isFloatTy() || Ty->isDoubleTy()) && !Subtarget->hasVFP2()) bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
if (isFloat && !Subtarget->hasVFP2())
return false; return false;
unsigned CmpOpc; unsigned CmpOpc;
@@ -1220,11 +1214,18 @@ bool ARMFastISel::ARMEmitCmp(Type *Ty, const Value *Src1Value,
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
.addReg(Src1).addReg(Src2)); .addReg(Src1).addReg(Src2));
// For floating point we need to move the result to a comparison register
// that we can then use for branches.
if (Ty->isFloatTy() || Ty->isDoubleTy())
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(ARM::FMSTAT)));
return true; return true;
} }
bool ARMFastISel::SelectCmp(const Instruction *I) { bool ARMFastISel::SelectCmp(const Instruction *I) {
const CmpInst *CI = cast<CmpInst>(I); const CmpInst *CI = cast<CmpInst>(I);
Type *Ty = CI->getOperand(0)->getType();
// Get the compare predicate. // Get the compare predicate.
ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate()); ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
@@ -1233,26 +1234,18 @@ bool ARMFastISel::SelectCmp(const Instruction *I) {
if (ARMPred == ARMCC::AL) return false; if (ARMPred == ARMCC::AL) return false;
// Emit the compare. // Emit the compare.
Type *Ty = CI->getOperand(0)->getType(); if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1)))
if (!ARMEmitCmp(Ty, CI->getOperand(0), CI->getOperand(1)))
return false; return false;
// For floating point we need to move the result to a comparison register
// that we can then use for branches.
bool isFloat = Ty->isFloatTy() || Ty->isDoubleTy();
if (isFloat)
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
TII.get(ARM::FMSTAT)));
// Now set a register based on the comparison. Explicitly set the predicates // Now set a register based on the comparison. Explicitly set the predicates
// here. // here.
unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi; unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi;
TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass
: ARM::GPRRegisterClass; : ARM::GPRRegisterClass;
unsigned DestReg = createResultReg(RC); unsigned DestReg = createResultReg(RC);
Constant *Zero Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
= ConstantInt::get(Type::getInt32Ty(*Context), 0);
unsigned ZeroReg = TargetMaterializeConstant(Zero); unsigned ZeroReg = TargetMaterializeConstant(Zero);
bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
unsigned CondReg = isFloat ? ARM::FPSCR : ARM::CPSR; unsigned CondReg = isFloat ? ARM::FPSCR : ARM::CPSR;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg) BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
.addReg(ZeroReg).addImm(1) .addReg(ZeroReg).addImm(1)