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Avoid modifying the OneClassForEachPhysReg map while iterating over it.

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Linear scan regalloc is currently assuming that any register aliased with
a member of a regclass must also be in at least one regclass.  That is not
always true.  For example, for X86, RIP is in a regclass but IP is not.
If you're unlucky, this can cause a crash by invalidating the iterator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124365 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2011-01-27 07:26:15 +00:00
parent f382f3b4dd
commit adf9c8b0e7
1 changed files with 6 additions and 2 deletions
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8
lib/CodeGen/RegAllocLinearScan.cpp
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@ -431,8 +431,12 @@ void RALinScan::ComputeRelatedRegClasses() {
for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
I != E; ++I)
for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS) {
const TargetRegisterClass *AliasClass =
OneClassForEachPhysReg.lookup(*AS);
if (AliasClass)
RelatedRegClasses.unionSets(I->second, AliasClass);
}
}
/// attemptTrivialCoalescing - If a simple interval is defined by a copy, try