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Avoid modifying the OneClassForEachPhysReg map while iterating over it.
Linear scan regalloc is currently assuming that any register aliased with a member of a regclass must also be in at least one regclass. That is not always true. For example, for X86, RIP is in a regclass but IP is not. If you're unlucky, this can cause a crash by invalidating the iterator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124365 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -431,8 +431,12 @@ void RALinScan::ComputeRelatedRegClasses() {
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for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
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for (DenseMap<unsigned, const TargetRegisterClass*>::iterator
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I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
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I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end();
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I != E; ++I)
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I != E; ++I)
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for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS)
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for (const unsigned *AS = tri_->getAliasSet(I->first); *AS; ++AS) {
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RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
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const TargetRegisterClass *AliasClass =
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OneClassForEachPhysReg.lookup(*AS);
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if (AliasClass)
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RelatedRegClasses.unionSets(I->second, AliasClass);
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}
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}
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}
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/// attemptTrivialCoalescing - If a simple interval is defined by a copy, try
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/// attemptTrivialCoalescing - If a simple interval is defined by a copy, try
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