From ae218dee5e3a079becd6b9b8d47e67cf814b9b70 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Wed, 29 Jun 2011 22:01:15 +0000 Subject: [PATCH] ARM RSCS* don't need explicit TableGen decoder checks. They've been pseudos for a while now, so the decoder will never see them in the first place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134101 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/TableGen/ARMDecoderEmitter.cpp | 4 ---- 1 file changed, 4 deletions(-) diff --git a/utils/TableGen/ARMDecoderEmitter.cpp b/utils/TableGen/ARMDecoderEmitter.cpp index cccfefde703..a320e77b287 100644 --- a/utils/TableGen/ARMDecoderEmitter.cpp +++ b/utils/TableGen/ARMDecoderEmitter.cpp @@ -1592,10 +1592,6 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI, // The following special cases are for conflict resolutions. // - // RSCSri and RSCSrs set the 's' bit, but are not predicated. We are - // better off using the generic RSCri and RSCrs instructions. - if (Name == "RSCSri" || Name == "RSCSrs") return false; - // A8-598: VEXT // Vector Extract extracts elements from the bottom end of the second // operand vector and the top end of the first, concatenates them and