From ae30bea9d74446ec9cc30fe3f639c1431d51bb9b Mon Sep 17 00:00:00 2001
From: Bradley Smith <bradley.smith@arm.com>
Date: Wed, 9 Apr 2014 14:44:26 +0000
Subject: [PATCH] [ARM64] Add missing shifted register MVN alias to ORN

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205891 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM64/ARM64InstrInfo.td                | 5 +++++
 lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp | 8 ++++++++
 test/MC/ARM64/aliases.s                           | 8 ++++++++
 3 files changed, 21 insertions(+)

diff --git a/lib/Target/ARM64/ARM64InstrInfo.td b/lib/Target/ARM64/ARM64InstrInfo.td
index 241ada9ca2d..ca0ff681786 100644
--- a/lib/Target/ARM64/ARM64InstrInfo.td
+++ b/lib/Target/ARM64/ARM64InstrInfo.td
@@ -624,6 +624,11 @@ def : InstAlias<"mvn $Wd, $Wm",
 def : InstAlias<"mvn $Xd, $Xm",
                 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0)>;
 
+def : InstAlias<"mvn $Wd, $Wm, $sh",
+                (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift:$sh)>;
+def : InstAlias<"mvn $Xd, $Xm, $sh",
+                (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift:$sh)>;
+
 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
 
diff --git a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
index 749cb5232ea..a10624a0f89 100644
--- a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
+++ b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
@@ -191,6 +191,14 @@ void ARM64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
     return;
   }
 
+  // ORN Wn, WZR, Wm{, lshift #imm} ==> MVN Wn, Wm{, lshift #imm}
+  // ORN Xn, XZR, Xm{, lshift #imm} ==> MVN Xn, Xm{, lshift #imm}
+  if ((Opcode == ARM64::ORNWrs && MI->getOperand(1).getReg() == ARM64::WZR) ||
+      (Opcode == ARM64::ORNXrs && MI->getOperand(1).getReg() == ARM64::XZR)) {
+    O << "\tmvn\t" << getRegisterName(MI->getOperand(0).getReg()) << ", ";
+    printShiftedRegister(MI, 2, O);
+    return;
+  }
   // SUBS WZR, Wn, #imm ==> CMP Wn, #imm
   // SUBS XZR, Xn, #imm ==> CMP Xn, #imm
   if ((Opcode == ARM64::SUBSWri && MI->getOperand(0).getReg() == ARM64::WZR) ||
diff --git a/test/MC/ARM64/aliases.s b/test/MC/ARM64/aliases.s
index b23f3e5ea08..f0d1d5d76a5 100644
--- a/test/MC/ARM64/aliases.s
+++ b/test/MC/ARM64/aliases.s
@@ -159,6 +159,14 @@ foo:
 ; CHECK: mvn	x2, x3             ; encoding: [0xe2,0x03,0x23,0xaa]
 ; CHECK: mvn	w4, w9             ; encoding: [0xe4,0x03,0x29,0x2a]
 
+        mvn w4, w9, lsl #1
+        mvn x2, x3, lsl #1
+        orn w4, wzr, w9, lsl #1
+
+; CHECK: mvn	w4, w9, lsl #1     ; encoding: [0xe4,0x07,0x29,0x2a]
+; CHECK: mvn	x2, x3, lsl #1     ; encoding: [0xe2,0x07,0x23,0xaa]
+; CHECK: mvn	w4, w9, lsl #1     ; encoding: [0xe4,0x07,0x29,0x2a]
+
 ;-----------------------------------------------------------------------------
 ; Bitfield aliases
 ;-----------------------------------------------------------------------------