mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-10-01 10:57:21 +00:00
Support for microMIPS FPU instructions 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198009 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic
parent
fab5704cef
commit
ae3597c141
@ -96,4 +96,53 @@ def FNEG_MM : MMRel, ABSS_FT<"neg.d", AFGR64Opnd, AFGR64Opnd, IIFcvt, fneg>,
|
||||
|
||||
def FMOV_D32_MM : MMRel, ABSS_FT<"mov.d", AFGR64Opnd, AFGR64Opnd, IIFmove>,
|
||||
ABS_FM_MM<1, 0x1>, Requires<[NotFP64bit, HasStdEnc]>;
|
||||
|
||||
def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, IIFmove>,
|
||||
CMov_I_F_FM_MM<0x78, 0>;
|
||||
def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, IIFmove>,
|
||||
CMov_I_F_FM_MM<0x38, 0>;
|
||||
def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
|
||||
IIFmove>, CMov_I_F_FM_MM<0x78, 1>;
|
||||
def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
|
||||
IIFmove>, CMov_I_F_FM_MM<0x38, 1>;
|
||||
|
||||
def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, IIFmove, MipsCMovFP_T>,
|
||||
CMov_F_F_FM_MM<0x60, 0>;
|
||||
def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, IIFmove, MipsCMovFP_F>,
|
||||
CMov_F_F_FM_MM<0x20, 0>;
|
||||
def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd,
|
||||
IIFmove, MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>;
|
||||
def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd,
|
||||
IIFmove, MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>;
|
||||
|
||||
def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, IIFmove>,
|
||||
MFC1_FM_MM<0x40>;
|
||||
def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, IIFmove>,
|
||||
MFC1_FM_MM<0x60>;
|
||||
def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,
|
||||
IIFmoveC1, bitconvert>, MFC1_FM_MM<0x80>;
|
||||
def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
|
||||
IIFmoveC1, bitconvert>, MFC1_FM_MM<0xa0>;
|
||||
def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, IIFmoveC1>,
|
||||
MFC1_FM_MM<3>;
|
||||
def MTHC1_MM : MMRel, MTC1_FT<"mthc1", FGRH32Opnd, GPR32Opnd, IIFmoveC1>,
|
||||
MFC1_FM_MM<7>;
|
||||
|
||||
def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, IIFmulSingle, fadd>,
|
||||
MADDS_FM_MM<0x1>;
|
||||
def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, IIFmulSingle, fsub>,
|
||||
MADDS_FM_MM<0x21>;
|
||||
def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, IIFmulSingle, fadd>,
|
||||
MADDS_FM_MM<0x2>;
|
||||
def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, IIFmulSingle, fsub>,
|
||||
MADDS_FM_MM<0x22>;
|
||||
|
||||
def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, IIFmulDouble, fadd>,
|
||||
MADDS_FM_MM<0x9>;
|
||||
def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, IIFmulDouble, fsub>,
|
||||
MADDS_FM_MM<0x29>;
|
||||
def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, IIFmulDouble,
|
||||
fadd>, MADDS_FM_MM<0xa>;
|
||||
def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, IIFmulDouble,
|
||||
fsub>, MADDS_FM_MM<0x2a>;
|
||||
}
|
||||
|
||||
@ -482,3 +482,63 @@ class ABS_FM_MM<bits<2> fmt, bits<7> funct> : MMArch {
|
||||
let Inst{12-6} = funct;
|
||||
let Inst{5-0} = 0x3b;
|
||||
}
|
||||
|
||||
class CMov_F_F_FM_MM<bits<9> func, bits<2> fmt> : MMArch {
|
||||
bits<5> fd;
|
||||
bits<5> fs;
|
||||
|
||||
bits<32> Inst;
|
||||
|
||||
let Inst{31-26} = 0x15;
|
||||
let Inst{25-21} = fd;
|
||||
let Inst{20-16} = fs;
|
||||
let Inst{15-13} = 0x0; //cc
|
||||
let Inst{12-11} = 0x0;
|
||||
let Inst{10-9} = fmt;
|
||||
let Inst{8-0} = func;
|
||||
}
|
||||
|
||||
class CMov_I_F_FM_MM<bits<8> funct, bits<2> fmt> : MMArch {
|
||||
bits<5> fd;
|
||||
bits<5> fs;
|
||||
bits<5> rt;
|
||||
|
||||
bits<32> Inst;
|
||||
|
||||
let Inst{31-26} = 0x15;
|
||||
let Inst{25-21} = rt;
|
||||
let Inst{20-16} = fs;
|
||||
let Inst{15-11} = fd;
|
||||
let Inst{9-8} = fmt;
|
||||
let Inst{7-0} = funct;
|
||||
}
|
||||
|
||||
class MFC1_FM_MM<bits<8> funct> : MMArch {
|
||||
bits<5> rt;
|
||||
bits<5> fs;
|
||||
|
||||
bits<32> Inst;
|
||||
|
||||
let Inst{31-26} = 0x15;
|
||||
let Inst{25-21} = rt;
|
||||
let Inst{20-16} = fs;
|
||||
let Inst{15-14} = 0x0;
|
||||
let Inst{13-6} = funct;
|
||||
let Inst{5-0} = 0x3b;
|
||||
}
|
||||
|
||||
class MADDS_FM_MM<bits<6> funct>: MMArch {
|
||||
bits<5> ft;
|
||||
bits<5> fs;
|
||||
bits<5> fd;
|
||||
bits<5> fr;
|
||||
|
||||
bits<32> Inst;
|
||||
|
||||
let Inst{31-26} = 0x15;
|
||||
let Inst{25-21} = ft;
|
||||
let Inst{20-16} = fs;
|
||||
let Inst{15-11} = fd;
|
||||
let Inst{10-6} = fr;
|
||||
let Inst{5-0} = funct;
|
||||
}
|
||||
|
||||
@ -27,7 +27,7 @@ class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
|
||||
class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
|
||||
InstrItinClass Itin> :
|
||||
InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
|
||||
!strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR> {
|
||||
!strconcat(opstr, "\t$fd, $fs, $rt"), [], Itin, FrmFR, opstr> {
|
||||
let Constraints = "$F = $fd";
|
||||
}
|
||||
|
||||
@ -47,7 +47,7 @@ class CMov_F_F_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
|
||||
InstSE<(outs RC:$fd), (ins RC:$fs, FCCRegsOpnd:$fcc, RC:$F),
|
||||
!strconcat(opstr, "\t$fd, $fs, $fcc"),
|
||||
[(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
|
||||
Itin, FrmFR> {
|
||||
Itin, FrmFR, opstr> {
|
||||
let Constraints = "$F = $fd";
|
||||
}
|
||||
|
||||
@ -127,14 +127,14 @@ let Predicates = [HasStdEnc], isCodeGenOnly = 1 in {
|
||||
ADD_FM<0, 0xb>;
|
||||
}
|
||||
|
||||
def MOVZ_I_S : CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, IIFmove>,
|
||||
def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, IIFmove>,
|
||||
CMov_I_F_FM<18, 16>;
|
||||
|
||||
let isCodeGenOnly = 1 in
|
||||
def MOVZ_I64_S : CMov_I_F_FT<"movz.s", GPR64Opnd, FGR32Opnd, IIFmove>,
|
||||
CMov_I_F_FM<18, 16>, Requires<[HasMips64, HasStdEnc]>;
|
||||
|
||||
def MOVN_I_S : CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, IIFmove>,
|
||||
def MOVN_I_S : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd, IIFmove>,
|
||||
CMov_I_F_FM<19, 16>;
|
||||
|
||||
let isCodeGenOnly = 1 in
|
||||
@ -142,10 +142,10 @@ def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, IIFmove>,
|
||||
CMov_I_F_FM<19, 16>, Requires<[HasMips64, HasStdEnc]>;
|
||||
|
||||
let Predicates = [NotFP64bit, HasStdEnc] in {
|
||||
def MOVZ_I_D32 : CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd, IIFmove>,
|
||||
CMov_I_F_FM<18, 17>;
|
||||
def MOVN_I_D32 : CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd, IIFmove>,
|
||||
CMov_I_F_FM<19, 17>;
|
||||
def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
|
||||
IIFmove>, CMov_I_F_FM<18, 17>;
|
||||
def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
|
||||
IIFmove>, CMov_I_F_FM<19, 17>;
|
||||
}
|
||||
|
||||
let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
|
||||
@ -175,16 +175,16 @@ let isCodeGenOnly = 1 in
|
||||
def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, IIArith, MipsCMovFP_F>,
|
||||
CMov_F_I_FM<0>, Requires<[HasMips64, HasStdEnc]>;
|
||||
|
||||
def MOVT_S : CMov_F_F_FT<"movt.s", FGR32Opnd, IIFmove, MipsCMovFP_T>,
|
||||
def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, IIFmove, MipsCMovFP_T>,
|
||||
CMov_F_F_FM<16, 1>;
|
||||
def MOVF_S : CMov_F_F_FT<"movf.s", FGR32Opnd, IIFmove, MipsCMovFP_F>,
|
||||
def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, IIFmove, MipsCMovFP_F>,
|
||||
CMov_F_F_FM<16, 0>;
|
||||
|
||||
let Predicates = [NotFP64bit, HasStdEnc] in {
|
||||
def MOVT_D32 : CMov_F_F_FT<"movt.d", AFGR64Opnd, IIFmove, MipsCMovFP_T>,
|
||||
CMov_F_F_FM<17, 1>;
|
||||
def MOVF_D32 : CMov_F_F_FT<"movf.d", AFGR64Opnd, IIFmove, MipsCMovFP_F>,
|
||||
CMov_F_F_FM<17, 0>;
|
||||
def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, IIFmove,
|
||||
MipsCMovFP_T>, CMov_F_F_FM<17, 1>;
|
||||
def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, IIFmove,
|
||||
MipsCMovFP_F>, CMov_F_F_FM<17, 0>;
|
||||
}
|
||||
|
||||
let Predicates = [IsFP64bit, HasStdEnc], DecoderNamespace = "Mips64" in {
|
||||
|
||||
@ -136,12 +136,12 @@ multiclass ROUND_M<string opstr, InstrItinClass Itin> {
|
||||
class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
|
||||
InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
|
||||
InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
|
||||
[(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR>;
|
||||
[(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>;
|
||||
|
||||
class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
|
||||
InstrItinClass Itin, SDPatternOperator OpNode= null_frag> :
|
||||
InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
|
||||
[(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR>;
|
||||
[(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>;
|
||||
|
||||
class LW_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
|
||||
SDPatternOperator OpNode= null_frag> :
|
||||
@ -163,14 +163,15 @@ class MADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
|
||||
SDPatternOperator OpNode = null_frag> :
|
||||
InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
|
||||
!strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
|
||||
[(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin, FrmFR>;
|
||||
[(set RC:$fd, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr))], Itin,
|
||||
FrmFR, opstr>;
|
||||
|
||||
class NMADDS_FT<string opstr, RegisterOperand RC, InstrItinClass Itin,
|
||||
SDPatternOperator OpNode = null_frag> :
|
||||
InstSE<(outs RC:$fd), (ins RC:$fr, RC:$fs, RC:$ft),
|
||||
!strconcat(opstr, "\t$fd, $fr, $fs, $ft"),
|
||||
[(set RC:$fd, (fsub fpimm0, (OpNode (fmul RC:$fs, RC:$ft), RC:$fr)))],
|
||||
Itin, FrmFR>;
|
||||
Itin, FrmFR, opstr>;
|
||||
|
||||
class LWXC1_FT<string opstr, RegisterOperand DRC,
|
||||
InstrItinClass Itin, SDPatternOperator OpNode = null_frag> :
|
||||
@ -337,15 +338,15 @@ defm FSQRT : ABSS_M<"sqrt.d", IIFsqrtDouble, fsqrt>, ABSS_FM<0x4, 17>;
|
||||
// regardless of register aliasing.
|
||||
|
||||
/// Move Control Registers From/To CPU Registers
|
||||
def CFC1 : MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, IIFmove>, MFC1_FM<2>;
|
||||
def CTC1 : MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, IIFmove>, MFC1_FM<6>;
|
||||
def MFC1 : MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, IIFmoveC1, bitconvert>,
|
||||
MFC1_FM<0>;
|
||||
def MTC1 : MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, IIFmoveC1, bitconvert>,
|
||||
MFC1_FM<4>;
|
||||
def MFHC1 : MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, IIFmoveC1>,
|
||||
def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, IIFmove>, MFC1_FM<2>;
|
||||
def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, IIFmove>, MFC1_FM<6>;
|
||||
def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, IIFmoveC1,
|
||||
bitconvert>, MFC1_FM<0>;
|
||||
def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, IIFmoveC1,
|
||||
bitconvert>, MFC1_FM<4>;
|
||||
def MFHC1 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, IIFmoveC1>,
|
||||
MFC1_FM<3>;
|
||||
def MTHC1 : MTC1_FT<"mthc1", FGRH32Opnd, GPR32Opnd, IIFmoveC1>,
|
||||
def MTHC1 : MMRel, MTC1_FT<"mthc1", FGRH32Opnd, GPR32Opnd, IIFmoveC1>,
|
||||
MFC1_FM<7>;
|
||||
def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, IIFmoveC1,
|
||||
bitconvert>, MFC1_FM<1>;
|
||||
@ -429,30 +430,30 @@ def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, IIFadd, 0, fsub>,
|
||||
defm FSUB : ADDS_M<"sub.d", IIFadd, 0, fsub>, ADDS_FM<0x01, 17>;
|
||||
|
||||
let Predicates = [HasMips32r2, HasStdEnc] in {
|
||||
def MADD_S : MADDS_FT<"madd.s", FGR32Opnd, IIFmulSingle, fadd>,
|
||||
def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, IIFmulSingle, fadd>,
|
||||
MADDS_FM<4, 0>;
|
||||
def MSUB_S : MADDS_FT<"msub.s", FGR32Opnd, IIFmulSingle, fsub>,
|
||||
def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, IIFmulSingle, fsub>,
|
||||
MADDS_FM<5, 0>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMips32r2, NoNaNsFPMath, HasStdEnc] in {
|
||||
def NMADD_S : NMADDS_FT<"nmadd.s", FGR32Opnd, IIFmulSingle, fadd>,
|
||||
def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, IIFmulSingle, fadd>,
|
||||
MADDS_FM<6, 0>;
|
||||
def NMSUB_S : NMADDS_FT<"nmsub.s", FGR32Opnd, IIFmulSingle, fsub>,
|
||||
def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, IIFmulSingle, fsub>,
|
||||
MADDS_FM<7, 0>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMips32r2, NotFP64bit, HasStdEnc] in {
|
||||
def MADD_D32 : MADDS_FT<"madd.d", AFGR64Opnd, IIFmulDouble, fadd>,
|
||||
def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, IIFmulDouble, fadd>,
|
||||
MADDS_FM<4, 1>;
|
||||
def MSUB_D32 : MADDS_FT<"msub.d", AFGR64Opnd, IIFmulDouble, fsub>,
|
||||
def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, IIFmulDouble, fsub>,
|
||||
MADDS_FM<5, 1>;
|
||||
}
|
||||
|
||||
let Predicates = [HasMips32r2, NotFP64bit, NoNaNsFPMath, HasStdEnc] in {
|
||||
def NMADD_D32 : NMADDS_FT<"nmadd.d", AFGR64Opnd, IIFmulDouble, fadd>,
|
||||
def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, IIFmulDouble, fadd>,
|
||||
MADDS_FM<6, 1>;
|
||||
def NMSUB_D32 : NMADDS_FT<"nmsub.d", AFGR64Opnd, IIFmulDouble, fsub>,
|
||||
def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, IIFmulDouble, fsub>,
|
||||
MADDS_FM<7, 1>;
|
||||
}
|
||||
|
||||
|
||||
@ -608,7 +608,7 @@ class ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch {
|
||||
let Inst{5-0} = funct;
|
||||
}
|
||||
|
||||
class MFC1_FM<bits<5> funct> {
|
||||
class MFC1_FM<bits<5> funct> : StdArch {
|
||||
bits<5> rt;
|
||||
bits<5> fs;
|
||||
|
||||
@ -714,7 +714,7 @@ class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
|
||||
let cond = c;
|
||||
}
|
||||
|
||||
class CMov_I_F_FM<bits<6> funct, bits<5> fmt> {
|
||||
class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch {
|
||||
bits<5> fd;
|
||||
bits<5> fs;
|
||||
bits<5> rt;
|
||||
@ -746,7 +746,7 @@ class CMov_F_I_FM<bit tf> : StdArch {
|
||||
let Inst{5-0} = 1;
|
||||
}
|
||||
|
||||
class CMov_F_F_FM<bits<5> fmt, bit tf> {
|
||||
class CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch {
|
||||
bits<5> fd;
|
||||
bits<5> fs;
|
||||
bits<3> fcc;
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
# RUN: llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips \
|
||||
# RUN: | FileCheck -check-prefix=CHECK-EL %s
|
||||
# RUN: -mcpu=mips32r2 | FileCheck -check-prefix=CHECK-EL %s
|
||||
# RUN: llvm-mc %s -triple=mips -show-encoding -mattr=micromips \
|
||||
# RUN: | FileCheck -check-prefix=CHECK-EB %s
|
||||
# RUN: -mcpu=mips32r2 | FileCheck -check-prefix=CHECK-EB %s
|
||||
# Check that the assembler can handle the documented syntax
|
||||
# for fpu instructions
|
||||
#------------------------------------------------------------------------------
|
||||
@ -49,6 +49,26 @@
|
||||
# CHECK-EL: cvt.d.w $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x33]
|
||||
# CHECK-EL: cvt.s.d $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x1b]
|
||||
# CHECK-EL: cvt.s.w $f6, $f8 # encoding: [0xc8,0x54,0x7b,0x3b]
|
||||
# CHECK-EL: cfc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x10]
|
||||
# CHECK-EL: ctc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x18]
|
||||
# CHECK-EL: mfc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x20]
|
||||
# CHECK-EL: mtc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x28]
|
||||
# CHECK-EL: movz.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x20]
|
||||
# CHECK-EL: movz.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x21]
|
||||
# CHECK-EL: movn.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x20]
|
||||
# CHECK-EL: movn.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x21]
|
||||
# CHECK-EL: movt.s $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x60,0x00]
|
||||
# CHECK-EL: movt.d $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x60,0x02]
|
||||
# CHECK-EL: movf.s $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x20,0x00]
|
||||
# CHECK-EL: movf.d $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x20,0x02]
|
||||
# CHECK-EL: madd.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x01,0x11]
|
||||
# CHECK-EL: madd.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x09,0x11]
|
||||
# CHECK-EL: msub.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x21,0x11]
|
||||
# CHECK-EL: msub.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x29,0x11]
|
||||
# CHECK-EL: nmadd.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x02,0x11]
|
||||
# CHECK-EL: nmadd.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x0a,0x11]
|
||||
# CHECK-EL: nmsub.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x22,0x11]
|
||||
# CHECK-EL: nmsub.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x2a,0x11]
|
||||
#------------------------------------------------------------------------------
|
||||
# Big endian
|
||||
#------------------------------------------------------------------------------
|
||||
@ -92,6 +112,26 @@
|
||||
# CHECK-EB: cvt.d.w $f6, $f8 # encoding: [0x54,0xc8,0x33,0x7b]
|
||||
# CHECK-EB: cvt.s.d $f6, $f8 # encoding: [0x54,0xc8,0x1b,0x7b]
|
||||
# CHECK-EB: cvt.s.w $f6, $f8 # encoding: [0x54,0xc8,0x3b,0x7b]
|
||||
# CHECK-EB: cfc1 $6, $0 # encoding: [0x54,0xc0,0x10,0x3b]
|
||||
# CHECK-EB: ctc1 $6, $0 # encoding: [0x54,0xc0,0x18,0x3b]
|
||||
# CHECK-EB: mfc1 $6, $f8 # encoding: [0x54,0xc8,0x20,0x3b]
|
||||
# CHECK-EB: mtc1 $6, $f8 # encoding: [0x54,0xc8,0x28,0x3b]
|
||||
# CHECK-EB: movz.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x78]
|
||||
# CHECK-EB: movz.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x78]
|
||||
# CHECK-EB: movn.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x38]
|
||||
# CHECK-EB: movn.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x38]
|
||||
# CHECK-EB: movt.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x60]
|
||||
# CHECK-EB: movt.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x60]
|
||||
# CHECK-EB: movf.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x20]
|
||||
# CHECK-EB: movf.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x20]
|
||||
# CHECK-EB: madd.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x01]
|
||||
# CHECK-EB: madd.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x09]
|
||||
# CHECK-EB: msub.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x21]
|
||||
# CHECK-EB: msub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x29]
|
||||
# CHECK-EB: nmadd.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x02]
|
||||
# CHECK-EB: nmadd.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x0a]
|
||||
# CHECK-EB: nmsub.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x22]
|
||||
# CHECK-EB: nmsub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x2a]
|
||||
|
||||
add.s $f4, $f6, $f8
|
||||
add.d $f4, $f6, $f8
|
||||
@ -131,3 +171,23 @@
|
||||
cvt.d.w $f6, $f8
|
||||
cvt.s.d $f6, $f8
|
||||
cvt.s.w $f6, $f8
|
||||
cfc1 $6, $0
|
||||
ctc1 $6, $0
|
||||
mfc1 $6, $f8
|
||||
mtc1 $6, $f8
|
||||
movz.s $f4, $f6, $7
|
||||
movz.d $f4, $f6, $7
|
||||
movn.s $f4, $f6, $7
|
||||
movn.d $f4, $f6, $7
|
||||
movt.s $f4, $f6, $fcc0
|
||||
movt.d $f4, $f6, $fcc0
|
||||
movf.s $f4, $f6, $fcc0
|
||||
movf.d $f4, $f6, $fcc0
|
||||
madd.s $f2, $f4, $f6, $f8
|
||||
madd.d $f2, $f4, $f6, $f8
|
||||
msub.s $f2, $f4, $f6, $f8
|
||||
msub.d $f2, $f4, $f6, $f8
|
||||
nmadd.s $f2, $f4, $f6, $f8
|
||||
nmadd.d $f2, $f4, $f6, $f8
|
||||
nmsub.s $f2, $f4, $f6, $f8
|
||||
nmsub.d $f2, $f4, $f6, $f8
|
||||
|
||||
Loading…
Reference in New Issue
Block a user