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https://github.com/c64scene-ar/llvm-6502.git
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TwoAddressInstructionPass refactoring: Extract another method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161284 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
@ -137,9 +137,10 @@ namespace {
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void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB,
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void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB,
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SmallPtrSet<MachineInstr*, 8> &Processed);
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SmallPtrSet<MachineInstr*, 8> &Processed);
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typedef SmallVector<std::pair<unsigned, unsigned>, 4> TiedOpList;
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typedef SmallVector<std::pair<unsigned, unsigned>, 4> TiedPairList;
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typedef SmallDenseMap<unsigned, TiedOpList> TiedOperandMap;
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typedef SmallDenseMap<unsigned, TiedPairList> TiedOperandMap;
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bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
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bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
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void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
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void CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, unsigned DstReg);
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void CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, unsigned DstReg);
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@ -1233,6 +1234,135 @@ collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) {
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return AnyOps;
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return AnyOps;
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}
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}
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// Process a list of tied MI operands that all use the same source register.
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// The tied pairs are of the form (SrcIdx, DstIdx).
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void
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TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
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TiedPairList &TiedPairs,
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unsigned &Dist) {
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bool IsEarlyClobber = false;
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bool RemovedKillFlag = false;
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bool AllUsesCopied = true;
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unsigned LastCopiedReg = 0;
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unsigned RegB = 0;
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for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
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unsigned SrcIdx = TiedPairs[tpi].first;
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unsigned DstIdx = TiedPairs[tpi].second;
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const MachineOperand &DstMO = MI->getOperand(DstIdx);
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unsigned RegA = DstMO.getReg();
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IsEarlyClobber |= DstMO.isEarlyClobber();
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// Grab RegB from the instruction because it may have changed if the
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// instruction was commuted.
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RegB = MI->getOperand(SrcIdx).getReg();
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if (RegA == RegB) {
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// The register is tied to multiple destinations (or else we would
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// not have continued this far), but this use of the register
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// already matches the tied destination. Leave it.
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AllUsesCopied = false;
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continue;
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}
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LastCopiedReg = RegA;
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assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
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"cannot make instruction into two-address form");
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#ifndef NDEBUG
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// First, verify that we don't have a use of "a" in the instruction
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// (a = b + a for example) because our transformation will not
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// work. This should never occur because we are in SSA form.
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for (unsigned i = 0; i != MI->getNumOperands(); ++i)
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assert(i == DstIdx ||
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!MI->getOperand(i).isReg() ||
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MI->getOperand(i).getReg() != RegA);
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#endif
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// Emit a copy.
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BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
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TII->get(TargetOpcode::COPY), RegA).addReg(RegB);
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// Update DistanceMap.
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MachineBasicBlock::iterator PrevMI = MI;
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--PrevMI;
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DistanceMap.insert(std::make_pair(PrevMI, Dist));
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DistanceMap[MI] = ++Dist;
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SlotIndex CopyIdx;
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if (Indexes)
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CopyIdx = Indexes->insertMachineInstrInMaps(PrevMI).getRegSlot();
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DEBUG(dbgs() << "\t\tprepend:\t" << *PrevMI);
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MachineOperand &MO = MI->getOperand(SrcIdx);
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assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
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"inconsistent operand info for 2-reg pass");
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if (MO.isKill()) {
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MO.setIsKill(false);
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RemovedKillFlag = true;
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}
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// Make sure regA is a legal regclass for the SrcIdx operand.
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if (TargetRegisterInfo::isVirtualRegister(RegA) &&
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TargetRegisterInfo::isVirtualRegister(RegB))
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MRI->constrainRegClass(RegA, MRI->getRegClass(RegB));
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MO.setReg(RegA);
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// Propagate SrcRegMap.
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SrcRegMap[RegA] = RegB;
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}
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if (AllUsesCopied) {
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if (!IsEarlyClobber) {
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// Replace other (un-tied) uses of regB with LastCopiedReg.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
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if (MO.isKill()) {
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MO.setIsKill(false);
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RemovedKillFlag = true;
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}
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MO.setReg(LastCopiedReg);
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}
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}
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}
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// Update live variables for regB.
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if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(MI)) {
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MachineBasicBlock::iterator PrevMI = MI;
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--PrevMI;
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LV->addVirtualRegisterKilled(RegB, PrevMI);
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}
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} else if (RemovedKillFlag) {
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// Some tied uses of regB matched their destination registers, so
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// regB is still used in this instruction, but a kill flag was
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// removed from a different tied use of regB, so now we need to add
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// a kill flag to one of the remaining uses of regB.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
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MO.setIsKill(true);
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break;
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}
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}
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}
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// We didn't change anything if there was a single tied pair, and that
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// pair didn't require copies.
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if (AllUsesCopied || TiedPairs.size() > 1) {
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// Schedule the source copy / remat inserted to form two-address
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// instruction. FIXME: Does it matter the distance map may not be
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// accurate after it's scheduled?
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MachineBasicBlock::iterator PrevMI = MI;
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--PrevMI;
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TII->scheduleTwoAddrSource(PrevMI, MI, *TRI);
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}
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}
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/// runOnMachineFunction - Reduce two-address instructions to two operands.
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/// runOnMachineFunction - Reduce two-address instructions to two operands.
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///
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///
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bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
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bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
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@ -1294,6 +1424,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
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}
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}
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++NumTwoAddressInstrs;
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++NumTwoAddressInstrs;
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MadeChange = true;
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DEBUG(dbgs() << '\t' << *mi);
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DEBUG(dbgs() << '\t' << *mi);
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// If the instruction has a single pair of tied operands, try some
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// If the instruction has a single pair of tied operands, try some
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@ -1322,125 +1453,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
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// Now iterate over the information collected above.
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// Now iterate over the information collected above.
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for (TiedOperandMap::iterator OI = TiedOperands.begin(),
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for (TiedOperandMap::iterator OI = TiedOperands.begin(),
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OE = TiedOperands.end(); OI != OE; ++OI) {
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OE = TiedOperands.end(); OI != OE; ++OI) {
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SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs = OI->second;
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processTiedPairs(mi, OI->second, Dist);
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bool IsEarlyClobber = false;
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bool RemovedKillFlag = false;
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bool AllUsesCopied = true;
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unsigned LastCopiedReg = 0;
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unsigned regB = OI->first;
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for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
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unsigned SrcIdx = TiedPairs[tpi].first;
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unsigned DstIdx = TiedPairs[tpi].second;
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const MachineOperand &DstMO = mi->getOperand(DstIdx);
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unsigned regA = DstMO.getReg();
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IsEarlyClobber |= DstMO.isEarlyClobber();
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// Grab regB from the instruction because it may have changed if the
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// instruction was commuted.
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regB = mi->getOperand(SrcIdx).getReg();
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if (regA == regB) {
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// The register is tied to multiple destinations (or else we would
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// not have continued this far), but this use of the register
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// already matches the tied destination. Leave it.
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AllUsesCopied = false;
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continue;
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}
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LastCopiedReg = regA;
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assert(TargetRegisterInfo::isVirtualRegister(regB) &&
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"cannot make instruction into two-address form");
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#ifndef NDEBUG
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// First, verify that we don't have a use of "a" in the instruction
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// (a = b + a for example) because our transformation will not
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// work. This should never occur because we are in SSA form.
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for (unsigned i = 0; i != mi->getNumOperands(); ++i)
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assert(i == DstIdx ||
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!mi->getOperand(i).isReg() ||
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mi->getOperand(i).getReg() != regA);
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#endif
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// Emit a copy.
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BuildMI(*mbbi, mi, mi->getDebugLoc(), TII->get(TargetOpcode::COPY),
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regA).addReg(regB);
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// Update DistanceMap.
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MachineBasicBlock::iterator prevMI = prior(mi);
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DistanceMap.insert(std::make_pair(prevMI, Dist));
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DistanceMap[mi] = ++Dist;
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SlotIndex CopyIdx;
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if (Indexes)
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CopyIdx = Indexes->insertMachineInstrInMaps(prevMI).getRegSlot();
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DEBUG(dbgs() << "\t\tprepend:\t" << *prevMI);
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MachineOperand &MO = mi->getOperand(SrcIdx);
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assert(MO.isReg() && MO.getReg() == regB && MO.isUse() &&
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"inconsistent operand info for 2-reg pass");
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if (MO.isKill()) {
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MO.setIsKill(false);
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RemovedKillFlag = true;
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}
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// Make sure regA is a legal regclass for the SrcIdx operand.
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if (TargetRegisterInfo::isVirtualRegister(regA) &&
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TargetRegisterInfo::isVirtualRegister(regB))
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MRI->constrainRegClass(regA, MRI->getRegClass(regB));
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MO.setReg(regA);
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// Propagate SrcRegMap.
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SrcRegMap[regA] = regB;
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}
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if (AllUsesCopied) {
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if (!IsEarlyClobber) {
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// Replace other (un-tied) uses of regB with LastCopiedReg.
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for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = mi->getOperand(i);
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if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
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if (MO.isKill()) {
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MO.setIsKill(false);
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RemovedKillFlag = true;
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}
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MO.setReg(LastCopiedReg);
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}
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}
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}
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// Update live variables for regB.
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if (RemovedKillFlag && LV && LV->getVarInfo(regB).removeKill(mi))
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LV->addVirtualRegisterKilled(regB, prior(mi));
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} else if (RemovedKillFlag) {
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// Some tied uses of regB matched their destination registers, so
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// regB is still used in this instruction, but a kill flag was
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// removed from a different tied use of regB, so now we need to add
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// a kill flag to one of the remaining uses of regB.
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for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = mi->getOperand(i);
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if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
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MO.setIsKill(true);
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break;
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}
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}
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}
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// We didn't change anything if there was a single tied pair, and that
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// pair didn't require copies.
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if (AllUsesCopied || TiedPairs.size() > 1) {
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MadeChange = true;
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// Schedule the source copy / remat inserted to form two-address
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// instruction. FIXME: Does it matter the distance map may not be
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// accurate after it's scheduled?
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TII->scheduleTwoAddrSource(prior(mi), mi, *TRI);
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}
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DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
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DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
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}
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}
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