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Merged from r214493:
[mips][PR19612] Fix va_arg for big-endian mode. Summary: Big-endian mode was not correctly adjusting the offset for types smaller than an ABI slot. Fixes PR19612 Reviewers: dsanders Reviewed By: dsanders Subscribers: sstankovic, llvm-commits Differential Revision: http://reviews.llvm.org/D4556 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@223007 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -251,7 +251,6 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM,
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setOperationAction(ISD::SETCC, MVT::f32, Custom);
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setOperationAction(ISD::SETCC, MVT::f64, Custom);
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setOperationAction(ISD::BRCOND, MVT::Other, Custom);
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setOperationAction(ISD::VASTART, MVT::Other, Custom);
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setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
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setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
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@ -343,7 +342,8 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM,
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setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
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setOperationAction(ISD::VAARG, MVT::Other, Expand);
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setOperationAction(ISD::VASTART, MVT::Other, Custom);
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setOperationAction(ISD::VAARG, MVT::Other, Custom);
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setOperationAction(ISD::VACOPY, MVT::Other, Expand);
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setOperationAction(ISD::VAEND, MVT::Other, Expand);
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@ -392,6 +392,11 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM,
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setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
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// The arguments on the stack are defined in terms of 4-byte slots on O32
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// and 8-byte slots on N32/N64.
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setMinStackArgumentAlignment(
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(Subtarget.isABI_N32() || Subtarget.isABI_N64()) ? 8 : 4);
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setStackPointerRegisterToSaveRestore(Subtarget.isABI_N64() ? Mips::SP_64
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: Mips::SP);
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@ -792,6 +797,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const
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case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG);
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case ISD::SETCC: return lowerSETCC(Op, DAG);
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case ISD::VASTART: return lowerVASTART(Op, DAG);
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case ISD::VAARG: return lowerVAARG(Op, DAG);
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case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
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case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
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case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
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@ -1755,6 +1761,65 @@ SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
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MachinePointerInfo(SV), false, false, 0);
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}
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SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
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SDNode *Node = Op.getNode();
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EVT VT = Node->getValueType(0);
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SDValue Chain = Node->getOperand(0);
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SDValue VAListPtr = Node->getOperand(1);
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unsigned Align = Node->getConstantOperandVal(3);
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const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
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SDLoc DL(Node);
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unsigned ArgSlotSizeInBytes =
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(Subtarget.isABI_N32() || Subtarget.isABI_N64()) ? 8 : 4;
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SDValue VAListLoad = DAG.getLoad(getPointerTy(), DL, Chain, VAListPtr,
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MachinePointerInfo(SV), false, false, false,
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0);
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SDValue VAList = VAListLoad;
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// Re-align the pointer if necessary.
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// It should only ever be necessary for 64-bit types on O32 since the minimum
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// argument alignment is the same as the maximum type alignment for N32/N64.
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//
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// FIXME: We currently align too often. The code generator doesn't notice
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// when the pointer is still aligned from the last va_arg (or pair of
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// va_args for the i64 on O32 case).
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if (Align > getMinStackArgumentAlignment()) {
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assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
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VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
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DAG.getConstant(Align - 1,
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VAList.getValueType()));
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VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
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DAG.getConstant(-(int64_t)Align,
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VAList.getValueType()));
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}
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// Increment the pointer, VAList, to the next vaarg.
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unsigned ArgSizeInBytes = getDataLayout()->getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
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SDValue Tmp3 = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
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DAG.getConstant(RoundUpToAlignment(ArgSizeInBytes, ArgSlotSizeInBytes),
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VAList.getValueType()));
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// Store the incremented VAList to the legalized pointer
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Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
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MachinePointerInfo(SV), false, false, 0);
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// In big-endian mode we must adjust the pointer when the load size is smaller
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// than the argument slot size. We must also reduce the known alignment to
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// match. For example in the N64 ABI, we must add 4 bytes to the offset to get
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// the correct half of the slot, and reduce the alignment from 8 (slot
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// alignment) down to 4 (type alignment).
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if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
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unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
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VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
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DAG.getIntPtrConstant(Adjustment));
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}
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// Load the actual argument out of the pointer VAList
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return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo(), false, false,
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false, 0);
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}
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static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
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bool HasExtractInsert) {
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EVT TyX = Op.getOperand(0).getValueType();
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@ -482,6 +482,7 @@ namespace llvm {
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SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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@ -4,11 +4,11 @@
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; RUN-TODO: llc -march=mips64 -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
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; RUN-TODO: llc -march=mips64el -relocation-model=static -mattr=-n64,+o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s
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; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=N32 --check-prefix=NEW %s
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; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=N32 --check-prefix=NEW %s
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; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=N32 --check-prefix=NEW --check-prefix=NEWBE %s
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; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=N32 --check-prefix=NEW --check-prefix=NEWLE %s
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; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=N64 --check-prefix=NEW %s
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; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=N64 --check-prefix=NEW %s
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; RUN: llc -march=mips64 -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=N64 --check-prefix=NEW --check-prefix=NEWBE %s
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; RUN: llc -march=mips64el -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=N64 --check-prefix=NEW --check-prefix=NEWLE %s
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; Test the effect of varargs on floating point types in the non-variable part
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; of the argument list as specified by section 2 of the MIPSpro N32 Handbook.
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@ -34,6 +34,7 @@ entry:
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%b = va_arg i8** %ap, double
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%1 = getelementptr [11 x double]* @doubles, i32 0, i32 2
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store volatile double %b, double* %1
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call void @llvm.va_end(i8* %ap2)
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ret void
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}
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@ -98,6 +99,7 @@ entry:
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%b = va_arg i8** %ap, float
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%1 = getelementptr [11 x float]* @floats, i32 0, i32 2
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store volatile float %b, float* %1
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call void @llvm.va_end(i8* %ap2)
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ret void
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}
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@ -140,16 +142,18 @@ entry:
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; Increment the pointer then get the varargs arg
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; LLVM will rebind the load to the stack pointer instead of the varargs pointer
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; during lowering. This is fine and doesn't change the behaviour.
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; N32/N64 is using ori instead of addiu/daddiu but (although odd) this is fine
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; since the stack is always aligned.
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; Also, in big-endian mode the offset must be increased by 4 to retrieve the
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; correct half of the argument slot.
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;
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; O32-DAG: addiu [[VAPTR]], [[VAPTR]], 4
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; O32-DAG: sw [[VAPTR]], 4($sp)
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; N32-DAG: ori [[VAPTR]], [[VAPTR]], 4
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; N32-DAG: addiu [[VAPTR]], [[VAPTR]], 8
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; N32-DAG: sw [[VAPTR]], 4($sp)
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; N64-DAG: ori [[VAPTR]], [[VAPTR]], 4
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; N64-DAG: daddiu [[VAPTR]], [[VAPTR]], 8
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; N64-DAG: sd [[VAPTR]], 0($sp)
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; O32-DAG: lwc1 [[FTMP1:\$f[0-9]+]], 12($sp)
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; NEW-DAG: lwc1 [[FTMP1:\$f[0-9]+]], 8($sp)
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; NEWLE-DAG: lwc1 [[FTMP1:\$f[0-9]+]], 8($sp)
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; NEWBE-DAG: lwc1 [[FTMP1:\$f[0-9]+]], 12($sp)
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; ALL-DAG: swc1 [[FTMP1]], 8([[R2]])
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declare void @llvm.va_start(i8*)
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1104
test/CodeGen/Mips/cconv/arguments-varargs.ll
Normal file
1104
test/CodeGen/Mips/cconv/arguments-varargs.ll
Normal file
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