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misched: Infrastructure for weak DAG edges.
This adds support for weak DAG edges to the general scheduling infrastructure in preparation for MachineScheduler support for heuristics based on weak edges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167738 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -111,9 +111,6 @@ namespace {
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/// added to the AvailableQueue.
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std::vector<SUnit*> PendingQueue;
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/// Topo - A topological ordering for SUnits.
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ScheduleDAGTopologicalSort Topo;
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/// HazardRec - The hazard recognizer to use.
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ScheduleHazardRecognizer *HazardRec;
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@@ -198,7 +195,7 @@ SchedulePostRATDList::SchedulePostRATDList(
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AliasAnalysis *AA, const RegisterClassInfo &RCI,
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TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
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SmallVectorImpl<const TargetRegisterClass*> &CriticalPathRCs)
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: ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), Topo(SUnits), AA(AA),
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: ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), AA(AA),
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LiveRegs(TRI->getNumRegs())
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{
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const TargetMachine &TM = MF.getTarget();
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@@ -580,10 +577,14 @@ void SchedulePostRATDList::FixupKills(MachineBasicBlock *MBB) {
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//===----------------------------------------------------------------------===//
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/// ReleaseSucc - Decrement the NumPredsLeft count of a successor. Add it to
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/// the PendingQueue if the count reaches zero. Also update its cycle bound.
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/// the PendingQueue if the count reaches zero.
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void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
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SUnit *SuccSU = SuccEdge->getSUnit();
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if (SuccEdge->isArtificial()) {
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--SuccSU->WeakPredsLeft;
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return;
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}
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#ifndef NDEBUG
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if (SuccSU->NumPredsLeft == 0) {
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dbgs() << "*** Scheduling failed! ***\n";
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@@ -653,8 +654,7 @@ void SchedulePostRATDList::ListScheduleTopDown() {
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// Add all leaves to Available queue.
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for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
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// It is available if it has no predecessors.
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bool available = SUnits[i].Preds.empty();
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if (available) {
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if (!SUnits[i].NumPredsLeft && !SUnits[i].isAvailable) {
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AvailableQueue.push(&SUnits[i]);
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SUnits[i].isAvailable = true;
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}
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