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[x86] Teach the new v4i32 shuffle lowering some more tricks to recognize
vzext patterns and insert-element patterns that for SSE4 have dedicated instructions. With this we can enable the experimental mode in a regression test that happens to cover some of the past set of issues. You can see that the new logic does significantly better here on the floating point cases. A follow-up to this change and the previous ones will hoist the logic into helpers so it can be shared across element type sizes as in this particular case it generalizes cleanly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217136 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -6840,6 +6840,13 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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// convert it to a vector with movd (S2V+shuffle to zero extend).
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Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
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Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
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// If using the new shuffle lowering, just directly insert this.
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if (ExperimentalVectorShuffleLowering)
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return DAG.getNode(
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ISD::BITCAST, dl, VT,
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getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
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Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
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// Now we have our 32-bit value zero extended in the low element of
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@ -6913,6 +6920,10 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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if (EVTBits == 32) {
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Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
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// If using the new shuffle lowering, just directly insert this.
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if (ExperimentalVectorShuffleLowering)
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return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
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// Turn it into a shuffle of zero and zero-extended scalar to vector.
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Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
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SmallVector<int, 8> MaskVec;
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@ -7492,7 +7503,10 @@ static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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ArrayRef<int> Mask = SVOp->getMask();
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assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
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if (isSingleInputShuffleMask(Mask))
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int NumV2Elements =
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std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
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if (NumV2Elements == 0)
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// Straight shuffle of a single input vector. For everything from SSE2
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// onward this has a single fast instruction with no scary immediates.
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return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
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@ -7504,6 +7518,52 @@ static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
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if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
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return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
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// There are special ways we can lower some single-element blends.
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if (NumV2Elements == 1) {
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int V2Index =
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std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
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Mask.begin();
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// Check for a single input from a SCALAR_TO_VECTOR node.
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// FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
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// all the smarts here sunk into that routine. However, the current
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// lowering of BUILD_VECTOR makes that nearly impossible until the old
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// vector shuffle lowering is dead.
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if ((Mask[V2Index] == 4 && V2.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
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V2.getOpcode() == ISD::BUILD_VECTOR) {
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SDValue V2S = V2.getOperand(Mask[V2Index] - 4);
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bool V1IsAllZero = false;
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if (ISD::isBuildVectorAllZeros(V1.getNode())) {
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V1IsAllZero = true;
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} else if (V1.getOpcode() == ISD::BUILD_VECTOR) {
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V1IsAllZero = true;
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for (int M : Mask) {
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if (M < 0 || M >= 4)
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continue;
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SDValue Input = V1.getOperand(M);
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if (Input.getOpcode() != ISD::UNDEF && !X86::isZeroNode(Input)) {
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// A non-zero input!
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V1IsAllZero = false;
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break;
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}
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}
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}
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if (V1IsAllZero) {
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V2 = DAG.getNode(
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X86ISD::VZEXT_MOVL, DL, MVT::v4i32,
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DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v4i32, V2S));
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if (V2Index != 0) {
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int V2Shuffle[] = {1, 1, 1, 1};
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V2Shuffle[V2Index] = 0;
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V2 = DAG.getVectorShuffle(MVT::v4i32, DL, V2,
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DAG.getUNDEF(MVT::v4i32), V2Shuffle);
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}
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return V2;
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}
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}
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}
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// We implement this with SHUFPS because it can blend from two vectors.
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// Because we're going to eventually use SHUFPS, we use SHUFPS even to build
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// up the inputs, bypassing domain shift penalties that we would encur if we
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@ -1,10 +1,15 @@
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; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=penryn | FileCheck %s
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; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=penryn -x86-experimental-vector-shuffle-lowering | FileCheck %s --check-prefix=CHECK-EXP
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define <4 x float> @test(float %a) {
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; CHECK-LABEL: test:
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; CHECK: movss {{.*}}, %xmm0
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1]
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; CHECK-NEXT: retl
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;
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; CHECK-EXP-LABEL: test:
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; CHECK-EXP: insertps $285, {{.*}}, %xmm0
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; CHECK-EXP-NEXT: retl
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entry:
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%tmp = insertelement <4 x float> zeroinitializer, float %a, i32 1
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@ -18,6 +23,11 @@ define <2 x i64> @test2(i32 %a) {
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; CHECK: movd {{.*}}, %xmm0
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,0,1]
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; CHECK-NEXT: retl
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;
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; CHECK-EXP-LABEL: test2:
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; CHECK-EXP: movd {{.*}}, %xmm0
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; CHECK-EXP-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,0,1]
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; CHECK-EXP-NEXT: retl
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entry:
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%tmp7 = insertelement <4 x i32> zeroinitializer, i32 %a, i32 2
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@ -32,6 +42,10 @@ define <4 x float> @test3(<4 x float> %A) {
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; CHECK-NEXT: movss %xmm0, %[[X1]]
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = [[X1]][1,0,1,1]
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; CHECK-NEXT: retl
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;
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; CHECK-EXP-LABEL: test3:
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; CHECK-EXP: insertps {{.*#+}} xmm0 = zero,xmm0[0],zero,zero
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; CHECK-EXP-NEXT: retl
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%tmp0 = extractelement <4 x float> %A, i32 0
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%tmp1 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef >, float %tmp0, i32 1
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@ -317,3 +317,52 @@ define <4 x float> @shuffle_v4f32_z6zz(<4 x float> %a) {
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%shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
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ret <4 x float> %shuffle
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}
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define <4 x i32> @shuffle_v4i32_4zzz(i32 %i) {
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; ALL-LABEL: @shuffle_v4i32_4zzz
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; ALL: movd {{.*}}, %xmm0
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; ALL-NEXT: retq
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%a = insertelement <4 x i32> undef, i32 %i, i32 0
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%shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
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ret <4 x i32> %shuffle
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}
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define <4 x i32> @shuffle_v4i32_z4zz(i32 %i) {
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; ALL-LABEL: @shuffle_v4i32_z4zz
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; ALL: movd {{.*}}, %xmm0
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; ALL-NEXT: pshufd {{.*}} # xmm0 = xmm0[1,0,1,1]
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; ALL-NEXT: retq
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%a = insertelement <4 x i32> undef, i32 %i, i32 0
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%shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 2, i32 4, i32 3, i32 0>
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ret <4 x i32> %shuffle
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}
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define <4 x i32> @shuffle_v4i32_zz4z(i32 %i) {
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; ALL-LABEL: @shuffle_v4i32_zz4z
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; ALL: movd {{.*}}, %xmm0
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; ALL-NEXT: pshufd {{.*}} # xmm0 = xmm0[1,1,0,1]
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; ALL-NEXT: retq
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%a = insertelement <4 x i32> undef, i32 %i, i32 0
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%shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 0, i32 0, i32 4, i32 0>
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ret <4 x i32> %shuffle
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}
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define <4 x i32> @shuffle_v4i32_zuu4(i32 %i) {
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; ALL-LABEL: @shuffle_v4i32_zuu4
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; ALL: movd {{.*}}, %xmm0
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; ALL-NEXT: pshufd {{.*}} # xmm0 = xmm0[1,1,1,0]
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; ALL-NEXT: retq
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%a = insertelement <4 x i32> undef, i32 %i, i32 0
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%shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 0, i32 undef, i32 undef, i32 4>
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ret <4 x i32> %shuffle
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}
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define <4 x i32> @shuffle_v4i32_z6zz(i32 %i) {
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; ALL-LABEL: @shuffle_v4i32_z6zz
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; ALL: movd {{.*}}, %xmm0
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; ALL-NEXT: pshufd {{.*}} # xmm0 = xmm0[1,0,1,1]
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; ALL-NEXT: retq
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%a = insertelement <4 x i32> undef, i32 %i, i32 2
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%shuffle = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
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ret <4 x i32> %shuffle
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}
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