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Make it SP, LR, PC for GPR Register Class instead of LR, SP, PC.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94465 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2010-01-25 22:54:29 +00:00
parent 44e87255e9
commit aeb326aad7
1 changed files with 1 additions and 1 deletions
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2
lib/Target/ARM/ARMRegisterInfo.td
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@ -124,7 +124,7 @@ def FPSCR : ARMReg<1, "fpscr">;
//
def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6,
R7, R8, R9, R10, R11, R12,
LR, SP, PC]> {
SP, LR, PC]> {
let MethodProtos = [{
iterator allocation_order_begin(const MachineFunction &MF) const;
iterator allocation_order_end(const MachineFunction &MF) const;