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Add vselect target support for targets that do not support blend but do support
xor/and/or (For example SSE2). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139623 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -61,6 +61,9 @@ class VectorLegalizer {
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// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
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// SINT_TO_FLOAT and SHR on vectors isn't legal.
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SDValue ExpandUINT_TO_FLOAT(SDValue Op);
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// Implement vselect in terms of XOR, AND,OR when blend is not supported
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// by the target.
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SDValue ExpandVSELECT(SDValue Op);
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SDValue ExpandFNEG(SDValue Op);
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// Implements vector promotion; this is essentially just bitcasting the
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// operands to a different type and bitcasting the result back to the
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@ -157,6 +160,7 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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case ISD::CTLZ:
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case ISD::CTPOP:
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case ISD::SELECT:
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case ISD::VSELECT:
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case ISD::SELECT_CC:
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case ISD::SETCC:
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case ISD::ZERO_EXTEND:
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@ -210,7 +214,9 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
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// FALL THROUGH
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}
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case TargetLowering::Expand:
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if (Node->getOpcode() == ISD::UINT_TO_FP)
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if (Node->getOpcode() == ISD::VSELECT)
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Result = ExpandVSELECT(Op);
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else if (Node->getOpcode() == ISD::UINT_TO_FP)
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Result = ExpandUINT_TO_FLOAT(Op);
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else if (Node->getOpcode() == ISD::FNEG)
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Result = ExpandFNEG(Op);
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@ -256,9 +262,42 @@ SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) {
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return DAG.getNode(ISD::BITCAST, dl, VT, Op);
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}
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SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
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// Implement VSELECT in terms of XOR, AND, OR
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// on platforms which do not support blend natively.
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EVT VT = Op.getOperand(0).getValueType();
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EVT OVT = Op.getOperand(0).getValueType();
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DebugLoc DL = Op.getDebugLoc();
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SDValue Mask = Op.getOperand(0);
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SDValue Op1 = Op.getOperand(1);
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SDValue Op2 = Op.getOperand(2);
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// If we can't even use the basic vector operations of
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// AND,OR,XOR, we will have to scalarize the op.
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if (!TLI.isOperationLegalOrCustom(ISD::AND, VT) ||
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!TLI.isOperationLegalOrCustom(ISD::XOR, VT) ||
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!TLI.isOperationLegalOrCustom(ISD::OR, VT)) {
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return DAG.UnrollVectorOp(Op.getNode());
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}
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assert(VT.getSizeInBits() == OVT.getSizeInBits() && "Invalid mask size");
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// Bitcast the operands to be the same type as the mask.
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// This is needed when we select between FP types because
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// the mask is a vector of integers.
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Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
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Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
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SDValue AllOnes = DAG.getConstant(
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APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), VT);
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SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
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Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
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Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
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return DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
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}
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SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
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EVT VT = Op.getOperand(0).getValueType();
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DebugLoc DL = Op.getDebugLoc();
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@ -6440,6 +6440,10 @@ SDValue SelectionDAG::UnrollVectorOp(SDNode *N, unsigned ResNE) {
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Scalars.push_back(getNode(N->getOpcode(), dl, EltVT,
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&Operands[0], Operands.size()));
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break;
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case ISD::VSELECT:
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Scalars.push_back(getNode(ISD::SELECT, dl, EltVT,
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&Operands[0], Operands.size()));
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break;
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case ISD::SHL:
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case ISD::SRA:
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case ISD::SRL:
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@ -727,6 +727,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
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setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
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setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
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setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
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for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
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InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
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setTruncStoreAction((MVT::SimpleValueType)VT,
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37
test/CodeGen/X86/sse2-blend.ll
Normal file
37
test/CodeGen/X86/sse2-blend.ll
Normal file
@ -0,0 +1,37 @@
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; RUN: llc < %s -march=x86 -mcpu=yonah -promote-elements -mattr=+sse2,-sse41
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define void@vsel_float(<4 x float>* %v1, <4 x float>* %v2) {
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%A = load <4 x float>* %v1
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%B = load <4 x float>* %v2
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %A, <4 x float> %B
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store <4 x float > %vsel, <4 x float>* %v1
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ret void
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}
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define void@vsel_i32(<4 x i32>* %v1, <4 x i32>* %v2) {
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%A = load <4 x i32>* %v1
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%B = load <4 x i32>* %v2
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %A, <4 x i32> %B
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store <4 x i32 > %vsel, <4 x i32>* %v1
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ret void
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}
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define void@vsel_i64(<4 x i64>* %v1, <4 x i64>* %v2) {
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%A = load <4 x i64>* %v1
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%B = load <4 x i64>* %v2
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i64> %A, <4 x i64> %B
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store <4 x i64 > %vsel, <4 x i64>* %v1
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ret void
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}
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define void@vsel_double(<4 x double>* %v1, <4 x double>* %v2) {
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%A = load <4 x double>* %v1
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%B = load <4 x double>* %v2
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x double> %A, <4 x double> %B
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store <4 x double > %vsel, <4 x double>* %v1
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ret void
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}
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