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Beginning of alloca implementation for Mips fast-isel
Summary: Begin to add various address modes; including alloca. Test Plan: Make sure there are no regressions in test-suite at O0/02 in mips32r1/r2 Reviewers: dsanders Reviewed By: dsanders Subscribers: echristo, rfuhler, llvm-commits Differential Revision: http://reviews.llvm.org/D6426 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230300 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler
parent
b664a60ecf
commit
aecbb87ee8
@ -2,6 +2,7 @@
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//---------------------===//
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#include "MipsCCState.h"
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#include "MipsInstrInfo.h"
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#include "MipsISelLowering.h"
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#include "MipsMachineFunction.h"
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#include "MipsRegisterInfo.h"
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@ -44,6 +45,7 @@ class MipsFastISel final : public FastISel {
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void setKind(BaseKind K) { Kind = K; }
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BaseKind getKind() const { return Kind; }
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bool isRegBase() const { return Kind == RegBase; }
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bool isFIBase() const { return Kind == FrameIndexBase; }
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void setReg(unsigned Reg) {
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assert(isRegBase() && "Invalid base register access!");
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Base.Reg = Reg;
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@ -52,6 +54,15 @@ class MipsFastISel final : public FastISel {
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assert(isRegBase() && "Invalid base register access!");
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return Base.Reg;
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}
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void setFI(unsigned FI) {
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assert(isFIBase() && "Invalid base frame index access!");
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Base.FI = FI;
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}
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unsigned getFI() const {
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assert(isFIBase() && "Invalid base frame index access!");
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return Base.FI;
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}
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void setOffset(int64_t Offset_) { Offset = Offset_; }
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int64_t getOffset() const { return Offset; }
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void setGlobalValue(const GlobalValue *G) { GV = G; }
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@ -94,6 +105,7 @@ private:
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bool isLoadTypeLegal(Type *Ty, MVT &VT);
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bool computeAddress(const Value *Obj, Address &Addr);
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bool computeCallAddress(const Value *V, Address &Addr);
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void simplifyAddress(Address &Addr);
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// Emit helper routines.
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bool emitCmp(unsigned DestReg, const CmpInst *CI);
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@ -304,14 +316,82 @@ unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
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}
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bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
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// This construct looks a big awkward but it is how other ports handle this
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// and as this function is more fully completed, these cases which
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// return false will have additional code in them.
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//
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if (isa<Instruction>(Obj))
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return false;
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else if (isa<ConstantExpr>(Obj))
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const User *U = nullptr;
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unsigned Opcode = Instruction::UserOp1;
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if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
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// Don't walk into other basic blocks unless the object is an alloca from
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// another block, otherwise it may not have a virtual register assigned.
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if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
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FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
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Opcode = I->getOpcode();
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U = I;
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}
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} else if (isa<ConstantExpr>(Obj))
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return false;
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switch (Opcode) {
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default:
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break;
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case Instruction::BitCast: {
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// Look through bitcasts.
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return computeAddress(U->getOperand(0), Addr);
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}
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case Instruction::GetElementPtr: {
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Address SavedAddr = Addr;
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uint64_t TmpOffset = Addr.getOffset();
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// Iterate through the GEP folding the constants into offsets where
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// we can.
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gep_type_iterator GTI = gep_type_begin(U);
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for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
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++i, ++GTI) {
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const Value *Op = *i;
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if (StructType *STy = dyn_cast<StructType>(*GTI)) {
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const StructLayout *SL = DL.getStructLayout(STy);
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unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
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TmpOffset += SL->getElementOffset(Idx);
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} else {
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uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
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for (;;) {
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if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
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// Constant-offset addressing.
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TmpOffset += CI->getSExtValue() * S;
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break;
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}
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if (canFoldAddIntoGEP(U, Op)) {
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// A compatible add with a constant operand. Fold the constant.
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ConstantInt *CI =
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cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
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TmpOffset += CI->getSExtValue() * S;
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// Iterate on the other operand.
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Op = cast<AddOperator>(Op)->getOperand(0);
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continue;
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}
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// Unsupported
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goto unsupported_gep;
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}
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}
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}
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// Try to grab the base operand now.
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Addr.setOffset(TmpOffset);
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if (computeAddress(U->getOperand(0), Addr))
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return true;
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// We failed, restore everything and try the other options.
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Addr = SavedAddr;
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unsupported_gep:
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break;
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}
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case Instruction::Alloca: {
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const AllocaInst *AI = cast<AllocaInst>(Obj);
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DenseMap<const AllocaInst *, int>::iterator SI =
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FuncInfo.StaticAllocaMap.find(AI);
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if (SI != FuncInfo.StaticAllocaMap.end()) {
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Addr.setKind(Address::FrameIndexBase);
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Addr.setFI(SI->second);
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return true;
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}
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break;
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}
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}
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Addr.setReg(getRegForValue(Obj));
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return Addr.getReg() != 0;
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}
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@ -517,8 +597,26 @@ bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
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default:
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return false;
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}
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emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
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return true;
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if (Addr.isRegBase()) {
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simplifyAddress(Addr);
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emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
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return true;
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}
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if (Addr.isFIBase()) {
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unsigned FI = Addr.getFI();
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unsigned Align = 4;
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unsigned Offset = Addr.getOffset();
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MachineFrameInfo &MFI = *MF->getFrameInfo();
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MachineMemOperand *MMO = MF->getMachineMemOperand(
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MachinePointerInfo::getFixedStack(FI), MachineMemOperand::MOLoad,
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MFI.getObjectSize(FI), Align);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
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.addFrameIndex(FI)
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.addImm(Offset)
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.addMemOperand(MMO);
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return true;
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}
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return false;
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}
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bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
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@ -550,8 +648,27 @@ bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
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default:
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return false;
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}
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emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
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return true;
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if (Addr.isRegBase()) {
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simplifyAddress(Addr);
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emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
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return true;
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}
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if (Addr.isFIBase()) {
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unsigned FI = Addr.getFI();
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unsigned Align = 4;
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unsigned Offset = Addr.getOffset();
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MachineFrameInfo &MFI = *MF->getFrameInfo();
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MachineMemOperand *MMO = MF->getMachineMemOperand(
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MachinePointerInfo::getFixedStack(FI), MachineMemOperand::MOLoad,
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MFI.getObjectSize(FI), Align);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
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.addReg(SrcReg)
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.addFrameIndex(FI)
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.addImm(Offset)
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.addMemOperand(MMO);
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return true;
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}
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return false;
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}
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bool MipsFastISel::selectLoad(const Instruction *I) {
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@ -970,15 +1087,6 @@ bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
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CLI.Call = MIB;
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// Add implicit physical register uses to the call.
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for (auto Reg : CLI.OutRegs)
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MIB.addReg(Reg, RegState::Implicit);
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// Add a register mask with the call-preserved registers. Proper
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// defs for return values will be added by setPhysRegsDeadExcept().
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MIB.addRegMask(TRI.getCallPreservedMask(CC));
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CLI.Call = MIB;
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// Finish off the call including any return values.
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return finishCall(CLI, RetVT, NumBytes);
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}
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@ -1243,6 +1351,17 @@ unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
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return VReg;
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}
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void MipsFastISel::simplifyAddress(Address &Addr) {
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if (!isInt<16>(Addr.getOffset())) {
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unsigned TempReg =
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materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
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unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
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emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
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Addr.setReg(DestReg);
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Addr.setOffset(0);
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}
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}
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namespace llvm {
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FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
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const TargetLibraryInfo *libInfo) {
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64
test/CodeGen/Mips/Fast-ISel/overflt.ll
Normal file
64
test/CodeGen/Mips/Fast-ISel/overflt.ll
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@ -0,0 +1,64 @@
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
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; RUN: < %s | FileCheck %s
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@x = common global [128000 x float] zeroinitializer, align 4
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@y = global float* getelementptr inbounds ([128000 x float]* @x, i32 0, i32 0), align 4
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@result = common global float 0.000000e+00, align 4
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@.str = private unnamed_addr constant [5 x i8] c"%f \0A\00", align 1
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; Function Attrs: nounwind
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define void @foo() {
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entry:
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; CHECK-LABEL: .ent foo
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%0 = load float** @y, align 4
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%arrayidx = getelementptr inbounds float* %0, i32 64000
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store float 5.500000e+00, float* %arrayidx, align 4
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; CHECK: lui $[[REG_FPCONST_INT:[0-9]+]], 16560
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; CHECK: mtc1 $[[REG_FPCONST_INT]], $f[[REG_FPCONST:[0-9]+]]
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; CHECK: lw $[[REG_Y_GOT:[0-9]+]], %got(y)(${{[0-9]+}})
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; CHECK: lw $[[REG_Y:[0-9]+]], 0($[[REG_Y_GOT]])
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; CHECK: lui $[[REG_IDX_UPPER:[0-9]+]], 3
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; CHECK: ori $[[REG_IDX:[0-9]+]], $[[REG_IDX_UPPER]], 59392
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; CHECK: addu $[[REG_Y_IDX:[0-9]+]], $[[REG_IDX]], $[[REG_Y]]
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; CHECK: swc1 $f[[REG_FPCONST]], 0($[[REG_Y_IDX]])
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ret void
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; CHECK-LABEL: .end foo
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}
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; Function Attrs: nounwind
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define void @goo() {
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entry:
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; CHECK-LABEL: .ent goo
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%0 = load float** @y, align 4
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%arrayidx = getelementptr inbounds float* %0, i32 64000
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%1 = load float* %arrayidx, align 4
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store float %1, float* @result, align 4
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; CHECK-DAG: lw $[[REG_RESULT:[0-9]+]], %got(result)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_Y_GOT:[0-9]+]], %got(y)(${{[0-9]+}})
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; CHECK-DAG: lw $[[REG_Y:[0-9]+]], 0($[[REG_Y_GOT]])
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; CHECK-DAG: lui $[[REG_IDX_UPPER:[0-9]+]], 3
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; CHECK-DAG: ori $[[REG_IDX:[0-9]+]], $[[REG_IDX_UPPER]], 59392
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; CHECK-DAG: addu $[[REG_Y_IDX:[0-9]+]], $[[REG_IDX]], $[[REG_Y]]
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; CHECK-DAG: lwc1 $f[[Y_IDX:[0-9]+]], 0($[[REG_Y_IDX]])
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; CHECK-DAG: swc1 $f[[Y_IDX]], 0($[[REG_RESULT]])
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; CHECK-LABEL: .end goo
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ret void
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}
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;
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; Original C code for test.
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;
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;float x[128000];
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;float *y = x;
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;float result;
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;void foo() {
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; y[64000] = 5.5;
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;}
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;void goo() {
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; result = y[64000];
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;}
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