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Teach PreprocessISelDAG to be aware of vector types and to not process them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136653 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -59,8 +59,8 @@ public:
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explicit X86FastISel(FunctionLoweringInfo &funcInfo) : FastISel(funcInfo) {
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Subtarget = &TM.getSubtarget<X86Subtarget>();
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StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
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X86ScalarSSEf64 = Subtarget->hasSSE2();
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X86ScalarSSEf32 = Subtarget->hasSSE1();
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X86ScalarSSEf64 = Subtarget->hasSSE2() || Subtarget->hasAVX();
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X86ScalarSSEf32 = Subtarget->hasSSE1() || Subtarget->hasAVX();
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}
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virtual bool TargetSelectInstruction(const Instruction *I);
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@ -474,10 +474,15 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
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if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
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continue;
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// If the source and destination are SSE registers, then this is a legal
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// conversion that should not be lowered.
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EVT SrcVT = N->getOperand(0).getValueType();
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EVT DstVT = N->getValueType(0);
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// If any of the sources are vectors, no fp stack involved.
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if (SrcVT.isVector() || DstVT.isVector())
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continue;
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// If the source and destination are SSE registers, then this is a legal
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// conversion that should not be lowered.
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bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
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bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
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if (SrcIsSSE && DstIsSSE)
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@ -168,8 +168,8 @@ static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
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X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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: TargetLowering(TM, createTLOF(TM)) {
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Subtarget = &TM.getSubtarget<X86Subtarget>();
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X86ScalarSSEf64 = Subtarget->hasXMMInt();
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X86ScalarSSEf32 = Subtarget->hasXMM();
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X86ScalarSSEf64 = Subtarget->hasXMMInt() || Subtarget->hasAVX();
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X86ScalarSSEf32 = Subtarget->hasXMM() || Subtarget->hasAVX();
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X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
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RegInfo = TM.getRegisterInfo();
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