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add conditional moves of float and double values on int/fp condition codes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25842 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -207,19 +207,18 @@ let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
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// scheduler into a branch sequence. This has to handle all permutations of
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// selection between i32/f32/f64 on ICC and FCC.
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let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
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let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
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Predicates = [HasNoV9] in { // V9 has conditional moves
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def SELECT_CC_Int_ICC
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
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"; SELECT_CC_Int_ICC PSEUDO!",
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[(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F,
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imm:$Cond, ICC))]>,
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Requires<[HasNoV9]>;
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imm:$Cond, ICC))]>;
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def SELECT_CC_Int_FCC
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
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"; SELECT_CC_Int_FCC PSEUDO!",
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[(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F,
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imm:$Cond, FCC))]>,
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Requires<[HasNoV9]>;
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imm:$Cond, FCC))]>;
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def SELECT_CC_FP_ICC
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: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_FP_ICC PSEUDO!",
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@ -566,7 +565,7 @@ class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
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// FIXME: the encoding for the JIT should look at the condition field.
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def FBCOND : FPBranchV8<0, (ops brtarget:$dst, V8CC:$cc),
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"f$cc $dst",
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"fb$cc $dst",
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[(V8brfcc bb:$dst, imm:$cc, FCC)]>;
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@ -748,6 +747,28 @@ let Predicates = [HasV9], isTwoAddress = 1 in {
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"movf$cc %fcc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selectfcc simm11:$F, IntRegs:$T, imm:$cc, FCC))]>;
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def FMOVS_ICC
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: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, V8CC:$cc),
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"fmovs$cc %icc, $F, $dst",
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[(set FPRegs:$dst,
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(V8selecticc FPRegs:$F, FPRegs:$T, imm:$cc, ICC))]>;
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def FMOVD_ICC
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: Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, V8CC:$cc),
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"fmovd$cc %icc, $F, $dst",
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[(set DFPRegs:$dst,
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(V8selecticc DFPRegs:$F, DFPRegs:$T, imm:$cc, ICC))]>;
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def FMOVS_FCC
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: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, V8CC:$cc),
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"fmovs$cc %fcc, $F, $dst",
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[(set FPRegs:$dst,
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(V8selectfcc FPRegs:$F, FPRegs:$T, imm:$cc, FCC))]>;
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def FMOVD_FCC
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: Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, V8CC:$cc),
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"fmovd$cc %fcc, $F, $dst",
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[(set DFPRegs:$dst,
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(V8selectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc, FCC))]>;
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}
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// Floating-Point Move Instructions, p. 164 of the V9 manual.
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@ -207,19 +207,18 @@ let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
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// scheduler into a branch sequence. This has to handle all permutations of
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// selection between i32/f32/f64 on ICC and FCC.
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let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
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let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
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Predicates = [HasNoV9] in { // V9 has conditional moves
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def SELECT_CC_Int_ICC
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
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"; SELECT_CC_Int_ICC PSEUDO!",
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[(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F,
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imm:$Cond, ICC))]>,
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Requires<[HasNoV9]>;
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imm:$Cond, ICC))]>;
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def SELECT_CC_Int_FCC
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: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
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"; SELECT_CC_Int_FCC PSEUDO!",
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[(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F,
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imm:$Cond, FCC))]>,
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Requires<[HasNoV9]>;
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imm:$Cond, FCC))]>;
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def SELECT_CC_FP_ICC
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: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
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"; SELECT_CC_FP_ICC PSEUDO!",
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@ -566,7 +565,7 @@ class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
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// FIXME: the encoding for the JIT should look at the condition field.
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def FBCOND : FPBranchV8<0, (ops brtarget:$dst, V8CC:$cc),
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"f$cc $dst",
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"fb$cc $dst",
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[(V8brfcc bb:$dst, imm:$cc, FCC)]>;
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@ -748,6 +747,28 @@ let Predicates = [HasV9], isTwoAddress = 1 in {
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"movf$cc %fcc, $F, $dst",
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[(set IntRegs:$dst,
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(V8selectfcc simm11:$F, IntRegs:$T, imm:$cc, FCC))]>;
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def FMOVS_ICC
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: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, V8CC:$cc),
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"fmovs$cc %icc, $F, $dst",
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[(set FPRegs:$dst,
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(V8selecticc FPRegs:$F, FPRegs:$T, imm:$cc, ICC))]>;
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def FMOVD_ICC
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: Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, V8CC:$cc),
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"fmovd$cc %icc, $F, $dst",
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[(set DFPRegs:$dst,
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(V8selecticc DFPRegs:$F, DFPRegs:$T, imm:$cc, ICC))]>;
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def FMOVS_FCC
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: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, V8CC:$cc),
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"fmovs$cc %fcc, $F, $dst",
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[(set FPRegs:$dst,
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(V8selectfcc FPRegs:$F, FPRegs:$T, imm:$cc, FCC))]>;
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def FMOVD_FCC
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: Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, V8CC:$cc),
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"fmovd$cc %fcc, $F, $dst",
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[(set DFPRegs:$dst,
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(V8selectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc, FCC))]>;
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}
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// Floating-Point Move Instructions, p. 164 of the V9 manual.
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