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https://github.com/c64scene-ar/llvm-6502.git
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ARM: Fix cttz expansion on vector types.
The 64/128-bit vector types are legal if NEON instructions are available. However, there was no matching patterns for @llvm.cttz.*() intrinsics and result in fatal error. This commit fixes the problem by lowering cttz to: a. ctpop((x & -x) - 1) b. width - ctlz(x & -x) - 1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242037 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Logan Chien
parent
f8560e5a5b
commit
af3e4a2f2f
@ -543,6 +543,27 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
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setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
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// NEON does not have single instruction CTTZ for vectors.
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setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
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setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
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setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
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setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
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setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
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setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
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setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
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setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
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setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
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// NEON only has FMA instructions as of VFP4.
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if (!Subtarget->hasVFP4()) {
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setOperationAction(ISD::FMA, MVT::v2f32, Expand);
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@ -4282,8 +4303,82 @@ SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
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static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
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const ARMSubtarget *ST) {
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EVT VT = N->getValueType(0);
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SDLoc dl(N);
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EVT VT = N->getValueType(0);
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if (VT.isVector()) {
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assert(ST->hasNEON());
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// Compute the least significant set bit: LSB = X & -X
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SDValue X = N->getOperand(0);
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SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X);
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SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX);
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EVT ElemTy = VT.getVectorElementType();
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if (ElemTy == MVT::i8) {
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// Compute with: cttz(x) = ctpop(lsb - 1)
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SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
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DAG.getTargetConstant(1, dl, ElemTy));
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SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
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return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
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}
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if ((ElemTy == MVT::i16 || ElemTy == MVT::i32) &&
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(N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) {
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// Compute with: cttz(x) = (width - 1) - ctlz(lsb), if x != 0
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unsigned NumBits = ElemTy.getSizeInBits();
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SDValue WidthMinus1 =
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DAG.getNode(ARMISD::VMOVIMM, dl, VT,
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DAG.getTargetConstant(NumBits - 1, dl, ElemTy));
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SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB);
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return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);
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}
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// Compute with: cttz(x) = ctpop(lsb - 1)
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// Since we can only compute the number of bits in a byte with vcnt.8, we
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// have to gather the result with pairwise addition (vpaddl) for i16, i32,
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// and i64.
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// Compute LSB - 1.
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SDValue Bits;
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if (ElemTy == MVT::i64) {
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// Load constant 0xffff'ffff'ffff'ffff to register.
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SDValue FF = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
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DAG.getTargetConstant(0x1eff, dl, MVT::i32));
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Bits = DAG.getNode(ISD::ADD, dl, VT, LSB, FF);
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} else {
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SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
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DAG.getTargetConstant(1, dl, ElemTy));
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Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
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}
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// Count #bits with vcnt.8.
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EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
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SDValue BitsVT8 = DAG.getNode(ISD::BITCAST, dl, VT8Bit, Bits);
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SDValue Cnt8 = DAG.getNode(ISD::CTPOP, dl, VT8Bit, BitsVT8);
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// Gather the #bits with vpaddl (pairwise add.)
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EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
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SDValue Cnt16 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT16Bit,
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DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
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Cnt8);
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if (ElemTy == MVT::i16)
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return Cnt16;
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EVT VT32Bit = VT.is64BitVector() ? MVT::v2i32 : MVT::v4i32;
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SDValue Cnt32 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT32Bit,
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DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
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Cnt16);
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if (ElemTy == MVT::i32)
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return Cnt32;
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assert(ElemTy == MVT::i64);
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SDValue Cnt64 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
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Cnt32);
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return Cnt64;
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}
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if (!ST->hasV6T2Ops())
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return SDValue();
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@ -6487,7 +6582,8 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
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case ISD::SRL_PARTS:
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case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
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case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
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case ISD::CTTZ:
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case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
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case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
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case ISD::SETCC: return LowerVSETCC(Op, DAG);
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case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
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90
test/CodeGen/ARM/cttz.ll
Normal file
90
test/CodeGen/ARM/cttz.ll
Normal file
@ -0,0 +1,90 @@
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; RUN: llc < %s -mtriple arm-eabi -mattr=+v6t2 | FileCheck %s
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; RUN: llc < %s -mtriple arm-eabi -mattr=+v6t2 -mattr=+neon | FileCheck %s
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; This test checks the @llvm.cttz.* intrinsics for integers.
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declare i8 @llvm.cttz.i8(i8, i1)
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declare i16 @llvm.cttz.i16(i16, i1)
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declare i32 @llvm.cttz.i32(i32, i1)
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declare i64 @llvm.cttz.i64(i64, i1)
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;------------------------------------------------------------------------------
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define i8 @test_i8(i8 %a) {
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; CHECK-LABEL: test_i8:
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; CHECK: orr [[REG:r[0-9]+]], [[REG]], #256
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; CHECK: rbit
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; CHECK: clz
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%tmp = call i8 @llvm.cttz.i8(i8 %a, i1 false)
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ret i8 %tmp
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}
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define i16 @test_i16(i16 %a) {
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; CHECK-LABEL: test_i16:
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; CHECK: orr [[REG:r[0-9]+]], [[REG]], #65536
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; CHECK: rbit
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; CHECK: clz
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%tmp = call i16 @llvm.cttz.i16(i16 %a, i1 false)
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ret i16 %tmp
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}
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define i32 @test_i32(i32 %a) {
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; CHECK-LABEL: test_i32:
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; CHECK: rbit
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; CHECK: clz
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%tmp = call i32 @llvm.cttz.i32(i32 %a, i1 false)
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ret i32 %tmp
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}
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define i64 @test_i64(i64 %a) {
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; CHECK-LABEL: test_i64:
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; CHECK: rbit
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; CHECK: rbit
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; CHECK: cmp
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; CHECK: clz
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; CHECK: add
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; CHECK: clzne
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%tmp = call i64 @llvm.cttz.i64(i64 %a, i1 false)
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ret i64 %tmp
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}
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;------------------------------------------------------------------------------
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define i8 @test_i8_zero_undef(i8 %a) {
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; CHECK-LABEL: test_i8_zero_undef:
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; CHECK-NOT: orr
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; CHECK: rbit
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; CHECK: clz
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%tmp = call i8 @llvm.cttz.i8(i8 %a, i1 true)
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ret i8 %tmp
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}
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define i16 @test_i16_zero_undef(i16 %a) {
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; CHECK-LABEL: test_i16_zero_undef:
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; CHECK-NOT: orr
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; CHECK: rbit
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; CHECK: clz
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%tmp = call i16 @llvm.cttz.i16(i16 %a, i1 true)
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ret i16 %tmp
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}
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define i32 @test_i32_zero_undef(i32 %a) {
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; CHECK-LABEL: test_i32_zero_undef:
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; CHECK: rbit
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; CHECK: clz
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%tmp = call i32 @llvm.cttz.i32(i32 %a, i1 true)
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ret i32 %tmp
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}
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define i64 @test_i64_zero_undef(i64 %a) {
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; CHECK-LABEL: test_i64_zero_undef:
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; CHECK: rbit
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; CHECK: rbit
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; CHECK: cmp
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; CHECK: clz
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; CHECK: add
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; CHECK: clzne
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%tmp = call i64 @llvm.cttz.i64(i64 %a, i1 true)
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ret i64 %tmp
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}
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383
test/CodeGen/ARM/cttz_vector.ll
Normal file
383
test/CodeGen/ARM/cttz_vector.ll
Normal file
@ -0,0 +1,383 @@
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; RUN: llc < %s -mtriple armv7-linux-gnueabihf -mattr=+neon | FileCheck %s
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; This test checks the @llvm.cttz.* intrinsics for vectors.
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declare <1 x i8> @llvm.cttz.v1i8(<1 x i8>, i1)
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declare <2 x i8> @llvm.cttz.v2i8(<2 x i8>, i1)
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declare <4 x i8> @llvm.cttz.v4i8(<4 x i8>, i1)
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declare <8 x i8> @llvm.cttz.v8i8(<8 x i8>, i1)
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declare <16 x i8> @llvm.cttz.v16i8(<16 x i8>, i1)
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declare <1 x i16> @llvm.cttz.v1i16(<1 x i16>, i1)
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declare <2 x i16> @llvm.cttz.v2i16(<2 x i16>, i1)
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declare <4 x i16> @llvm.cttz.v4i16(<4 x i16>, i1)
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declare <8 x i16> @llvm.cttz.v8i16(<8 x i16>, i1)
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declare <1 x i32> @llvm.cttz.v1i32(<1 x i32>, i1)
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declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1)
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declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1)
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declare <1 x i64> @llvm.cttz.v1i64(<1 x i64>, i1)
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declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1)
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;------------------------------------------------------------------------------
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define void @test_v1i8(<1 x i8>* %p) {
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; CHECK-LABEL: test_v1i8
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%a = load <1 x i8>, <1 x i8>* %p
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%tmp = call <1 x i8> @llvm.cttz.v1i8(<1 x i8> %a, i1 false)
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store <1 x i8> %tmp, <1 x i8>* %p
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ret void
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}
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define void @test_v2i8(<2 x i8>* %p) {
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; CHECK-LABEL: test_v2i8:
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%a = load <2 x i8>, <2 x i8>* %p
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%tmp = call <2 x i8> @llvm.cttz.v2i8(<2 x i8> %a, i1 false)
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store <2 x i8> %tmp, <2 x i8>* %p
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ret void
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}
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define void @test_v4i8(<4 x i8>* %p) {
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; CHECK-LABEL: test_v4i8:
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%a = load <4 x i8>, <4 x i8>* %p
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%tmp = call <4 x i8> @llvm.cttz.v4i8(<4 x i8> %a, i1 false)
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store <4 x i8> %tmp, <4 x i8>* %p
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ret void
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}
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define void @test_v8i8(<8 x i8>* %p) {
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; CHECK-LABEL: test_v8i8:
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; CHECK: vldr [[D1:d[0-9]+]], [r0]
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; CHECK: vmov.i8 [[D2:d[0-9]+]], #0x1
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; CHECK: vneg.s8 [[D3:d[0-9]+]], [[D1]]
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; CHECK: vand [[D1]], [[D1]], [[D3]]
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; CHECK: vsub.i8 [[D1]], [[D1]], [[D2]]
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; CHECK: vcnt.8 [[D1]], [[D1]]
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; CHECK: vstr [[D1]], [r0]
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%a = load <8 x i8>, <8 x i8>* %p
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%tmp = call <8 x i8> @llvm.cttz.v8i8(<8 x i8> %a, i1 false)
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store <8 x i8> %tmp, <8 x i8>* %p
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ret void
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}
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define void @test_v16i8(<16 x i8>* %p) {
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; CHECK-LABEL: test_v16i8:
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; CHECK: vld1.64 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [r0]
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; CHECK: vmov.i8 [[Q2:q[0-9]+]], #0x1
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; CHECK: vneg.s8 [[Q3:q[0-9]+]], [[Q1:q[0-9]+]]
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; CHECK: vand [[Q1]], [[Q1]], [[Q3]]
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; CHECK: vsub.i8 [[Q1]], [[Q1]], [[Q2]]
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; CHECK: vcnt.8 [[Q1]], [[Q1]]
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; CHECK: vst1.64 {[[D1]], [[D2]]}, [r0]
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%a = load <16 x i8>, <16 x i8>* %p
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%tmp = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %a, i1 false)
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store <16 x i8> %tmp, <16 x i8>* %p
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ret void
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}
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define void @test_v1i16(<1 x i16>* %p) {
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; CHECK-LABEL: test_v1i16:
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%a = load <1 x i16>, <1 x i16>* %p
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%tmp = call <1 x i16> @llvm.cttz.v1i16(<1 x i16> %a, i1 false)
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store <1 x i16> %tmp, <1 x i16>* %p
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ret void
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}
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define void @test_v2i16(<2 x i16>* %p) {
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; CHECK-LABEL: test_v2i16:
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%a = load <2 x i16>, <2 x i16>* %p
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%tmp = call <2 x i16> @llvm.cttz.v2i16(<2 x i16> %a, i1 false)
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store <2 x i16> %tmp, <2 x i16>* %p
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ret void
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}
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define void @test_v4i16(<4 x i16>* %p) {
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; CHECK-LABEL: test_v4i16:
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; CHECK: vldr [[D1:d[0-9]+]], [r0]
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; CHECK: vmov.i16 [[D2:d[0-9]+]], #0x1
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; CHECK: vneg.s16 [[D3:d[0-9]+]], [[D1]]
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; CHECK: vand [[D1]], [[D1]], [[D3]]
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; CHECK: vsub.i16 [[D1]], [[D1]], [[D2]]
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; CHECK: vcnt.8 [[D1]], [[D1]]
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; CHECK: vpaddl.u8 [[D1]], [[D1]]
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; CHECK: vstr [[D1]], [r0]
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%a = load <4 x i16>, <4 x i16>* %p
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%tmp = call <4 x i16> @llvm.cttz.v4i16(<4 x i16> %a, i1 false)
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store <4 x i16> %tmp, <4 x i16>* %p
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ret void
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}
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define void @test_v8i16(<8 x i16>* %p) {
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; CHECK-LABEL: test_v8i16:
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; CHECK: vld1.64 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [r0]
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; CHECK: vmov.i16 [[Q2:q[0-9]+]], #0x1
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; CHECK: vneg.s16 [[Q3:q[0-9]+]], [[Q1:q[0-9]+]]
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; CHECK: vand [[Q1]], [[Q1]], [[Q3]]
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; CHECK: vsub.i16 [[Q1]], [[Q1]], [[Q2]]
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; CHECK: vcnt.8 [[Q1]], [[Q1]]
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; CHECK: vpaddl.u8 [[Q1]], [[Q1]]
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; CHECK: vst1.64 {[[D1]], [[D2]]}, [r0]
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%a = load <8 x i16>, <8 x i16>* %p
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%tmp = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %a, i1 false)
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store <8 x i16> %tmp, <8 x i16>* %p
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ret void
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}
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define void @test_v1i32(<1 x i32>* %p) {
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; CHECK-LABEL: test_v1i32:
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%a = load <1 x i32>, <1 x i32>* %p
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%tmp = call <1 x i32> @llvm.cttz.v1i32(<1 x i32> %a, i1 false)
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store <1 x i32> %tmp, <1 x i32>* %p
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ret void
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}
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define void @test_v2i32(<2 x i32>* %p) {
|
||||
; CHECK-LABEL: test_v2i32:
|
||||
; CHECK: vldr [[D1:d[0-9]+]], [r0]
|
||||
; CHECK: vmov.i32 [[D2:d[0-9]+]], #0x1
|
||||
; CHECK: vneg.s32 [[D3:d[0-9]+]], [[D1]]
|
||||
; CHECK: vand [[D1]], [[D1]], [[D3]]
|
||||
; CHECK: vsub.i32 [[D1]], [[D1]], [[D2]]
|
||||
; CHECK: vcnt.8 [[D1]], [[D1]]
|
||||
; CHECK: vpaddl.u8 [[D1]], [[D1]]
|
||||
; CHECK: vpaddl.u16 [[D1]], [[D1]]
|
||||
; CHECK: vstr [[D1]], [r0]
|
||||
%a = load <2 x i32>, <2 x i32>* %p
|
||||
%tmp = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %a, i1 false)
|
||||
store <2 x i32> %tmp, <2 x i32>* %p
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_v4i32(<4 x i32>* %p) {
|
||||
; CHECK-LABEL: test_v4i32:
|
||||
; CHECK: vld1.64 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [r0]
|
||||
; CHECK: vmov.i32 [[Q2:q[0-9]+]], #0x1
|
||||
; CHECK: vneg.s32 [[Q3:q[0-9]+]], [[Q1:q[0-9]+]]
|
||||
; CHECK: vand [[Q1]], [[Q1]], [[Q3]]
|
||||
; CHECK: vsub.i32 [[Q1]], [[Q1]], [[Q2]]
|
||||
; CHECK: vcnt.8 [[Q1]], [[Q1]]
|
||||
; CHECK: vpaddl.u8 [[Q1]], [[Q1]]
|
||||
; CHECK: vpaddl.u16 [[Q1]], [[Q1]]
|
||||
; CHECK: vst1.64 {[[D1]], [[D2]]}, [r0]
|
||||
%a = load <4 x i32>, <4 x i32>* %p
|
||||
%tmp = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %a, i1 false)
|
||||
store <4 x i32> %tmp, <4 x i32>* %p
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_v1i64(<1 x i64>* %p) {
|
||||
; CHECK-LABEL: test_v1i64:
|
||||
; CHECK: vldr [[D1:d[0-9]+]], [r0]
|
||||
; CHECK: vmov.i32 [[D2:d[0-9]+]], #0x0
|
||||
; CHECK: vmov.i64 [[D3:d[0-9]+]], #0xffffffffffffffff
|
||||
; CHECK: vsub.i64 [[D2]], [[D2]], [[D1]]
|
||||
; CHECK: vand [[D1]], [[D1]], [[D2]]
|
||||
; CHECK: vadd.i64 [[D1]], [[D1]], [[D3]]
|
||||
; CHECK: vcnt.8 [[D1]], [[D1]]
|
||||
; CHECK: vpaddl.u8 [[D1]], [[D1]]
|
||||
; CHECK: vpaddl.u16 [[D1]], [[D1]]
|
||||
; CHECK: vpaddl.u32 [[D1]], [[D1]]
|
||||
; CHECK: vstr [[D1]], [r0]
|
||||
%a = load <1 x i64>, <1 x i64>* %p
|
||||
%tmp = call <1 x i64> @llvm.cttz.v1i64(<1 x i64> %a, i1 false)
|
||||
store <1 x i64> %tmp, <1 x i64>* %p
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_v2i64(<2 x i64>* %p) {
|
||||
; CHECK-LABEL: test_v2i64:
|
||||
; CHECK: vld1.64 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [r0]
|
||||
; CHECK: vmov.i32 [[Q2:q[0-9]+]], #0x0
|
||||
; CHECK: vmov.i64 [[Q3:q[0-9]+]], #0xffffffffffffffff
|
||||
; CHECK: vsub.i64 [[Q2]], [[Q2]], [[Q1:q[0-9]+]]
|
||||
; CHECK: vand [[Q1]], [[Q1]], [[Q2]]
|
||||
; CHECK: vadd.i64 [[Q1]], [[Q1]], [[Q3]]
|
||||
; CHECK: vcnt.8 [[Q1]], [[Q1]]
|
||||
; CHECK: vpaddl.u8 [[Q1]], [[Q1]]
|
||||
; CHECK: vpaddl.u16 [[Q1]], [[Q1]]
|
||||
; CHECK: vpaddl.u32 [[Q1]], [[Q1]]
|
||||
; CHECK: vst1.64 {[[D1]], [[D2]]}, [r0]
|
||||
%a = load <2 x i64>, <2 x i64>* %p
|
||||
%tmp = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 false)
|
||||
store <2 x i64> %tmp, <2 x i64>* %p
|
||||
ret void
|
||||
}
|
||||
|
||||
;------------------------------------------------------------------------------
|
||||
|
||||
define void @test_v1i8_zero_undef(<1 x i8>* %p) {
|
||||
; CHECK-LABEL: test_v1i8_zero_undef
|
||||
%a = load <1 x i8>, <1 x i8>* %p
|
||||
%tmp = call <1 x i8> @llvm.cttz.v1i8(<1 x i8> %a, i1 true)
|
||||
store <1 x i8> %tmp, <1 x i8>* %p
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_v2i8_zero_undef(<2 x i8>* %p) {
|
||||
; CHECK-LABEL: test_v2i8_zero_undef:
|
||||
%a = load <2 x i8>, <2 x i8>* %p
|
||||
%tmp = call <2 x i8> @llvm.cttz.v2i8(<2 x i8> %a, i1 true)
|
||||
store <2 x i8> %tmp, <2 x i8>* %p
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_v4i8_zero_undef(<4 x i8>* %p) {
|
||||
; CHECK-LABEL: test_v4i8_zero_undef:
|
||||
%a = load <4 x i8>, <4 x i8>* %p
|
||||
%tmp = call <4 x i8> @llvm.cttz.v4i8(<4 x i8> %a, i1 true)
|
||||
store <4 x i8> %tmp, <4 x i8>* %p
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_v8i8_zero_undef(<8 x i8>* %p) {
|
||||
; CHECK-LABEL: test_v8i8_zero_undef:
|
||||
; CHECK: vldr [[D1:d[0-9]+]], [r0]
|
||||
; CHECK: vmov.i8 [[D2:d[0-9]+]], #0x1
|
||||
; CHECK: vneg.s8 [[D3:d[0-9]+]], [[D1]]
|
||||
; CHECK: vand [[D1]], [[D1]], [[D3]]
|
||||
; CHECK: vsub.i8 [[D1]], [[D1]], [[D2]]
|
||||
; CHECK: vcnt.8 [[D1]], [[D1]]
|
||||
; CHECK: vstr [[D1]], [r0]
|
||||
%a = load <8 x i8>, <8 x i8>* %p
|
||||
%tmp = call <8 x i8> @llvm.cttz.v8i8(<8 x i8> %a, i1 true)
|
||||
store <8 x i8> %tmp, <8 x i8>* %p
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_v16i8_zero_undef(<16 x i8>* %p) {
|
||||
; CHECK-LABEL: test_v16i8_zero_undef:
|
||||
; CHECK: vld1.64 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [r0]
|
||||
; CHECK: vmov.i8 [[Q2:q[0-9]+]], #0x1
|
||||
; CHECK: vneg.s8 [[Q3:q[0-9]+]], [[Q1:q[0-9]+]]
|
||||
; CHECK: vand [[Q1]], [[Q1]], [[Q3]]
|
||||
; CHECK: vsub.i8 [[Q1]], [[Q1]], [[Q2]]
|
||||
; CHECK: vcnt.8 [[Q1]], [[Q1]]
|
||||
; CHECK: vst1.64 {[[D1]], [[D2]]}, [r0]
|
||||
%a = load <16 x i8>, <16 x i8>* %p
|
||||
%tmp = call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %a, i1 true)
|
||||
store <16 x i8> %tmp, <16 x i8>* %p
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_v1i16_zero_undef(<1 x i16>* %p) {
|
||||
; CHECK-LABEL: test_v1i16_zero_undef:
|
||||
%a = load <1 x i16>, <1 x i16>* %p
|
||||
%tmp = call <1 x i16> @llvm.cttz.v1i16(<1 x i16> %a, i1 true)
|
||||
store <1 x i16> %tmp, <1 x i16>* %p
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_v2i16_zero_undef(<2 x i16>* %p) {
|
||||
; CHECK-LABEL: test_v2i16_zero_undef:
|
||||
%a = load <2 x i16>, <2 x i16>* %p
|
||||
%tmp = call <2 x i16> @llvm.cttz.v2i16(<2 x i16> %a, i1 true)
|
||||
store <2 x i16> %tmp, <2 x i16>* %p
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_v4i16_zero_undef(<4 x i16>* %p) {
|
||||
; CHECK-LABEL: test_v4i16_zero_undef:
|
||||
; CHECK: vldr [[D1:d[0-9]+]], [r0]
|
||||
; CHECK: vneg.s16 [[D2:d[0-9]+]], [[D1]]
|
||||
; CHECK: vand [[D1]], [[D1]], [[D2]]
|
||||
; CHECK: vmov.i16 [[D3:d[0-9]+]], #0xf
|
||||
; CHECK: vclz.i16 [[D1]], [[D1]]
|
||||
; CHECK: vsub.i16 [[D1]], [[D3]], [[D1]]
|
||||
; CHECK: vstr [[D1]], [r0]
|
||||
%a = load <4 x i16>, <4 x i16>* %p
|
||||
%tmp = call <4 x i16> @llvm.cttz.v4i16(<4 x i16> %a, i1 true)
|
||||
store <4 x i16> %tmp, <4 x i16>* %p
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_v8i16_zero_undef(<8 x i16>* %p) {
|
||||
; CHECK-LABEL: test_v8i16_zero_undef:
|
||||
; CHECK: vld1.64 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [r0]
|
||||
; CHECK: vneg.s16 [[Q2:q[0-9]+]], [[Q1:q[0-9]+]]
|
||||
; CHECK: vand [[Q1]], [[Q1]], [[Q2]]
|
||||
; CHECK: vmov.i16 [[Q3:q[0-9]+]], #0xf
|
||||
; CHECK: vclz.i16 [[Q1]], [[Q1]]
|
||||
; CHECK: vsub.i16 [[Q1]], [[Q3]], [[Q1]]
|
||||
; CHECK: vst1.64 {[[D1]], [[D2]]}, [r0]
|
||||
%a = load <8 x i16>, <8 x i16>* %p
|
||||
%tmp = call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %a, i1 true)
|
||||
store <8 x i16> %tmp, <8 x i16>* %p
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_v1i32_zero_undef(<1 x i32>* %p) {
|
||||
; CHECK-LABEL: test_v1i32_zero_undef:
|
||||
%a = load <1 x i32>, <1 x i32>* %p
|
||||
%tmp = call <1 x i32> @llvm.cttz.v1i32(<1 x i32> %a, i1 true)
|
||||
store <1 x i32> %tmp, <1 x i32>* %p
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_v2i32_zero_undef(<2 x i32>* %p) {
|
||||
; CHECK-LABEL: test_v2i32_zero_undef:
|
||||
; CHECK: vldr [[D1:d[0-9]+]], [r0]
|
||||
; CHECK: vneg.s32 [[D2:d[0-9]+]], [[D1]]
|
||||
; CHECK: vand [[D1]], [[D1]], [[D2]]
|
||||
; CHECK: vmov.i32 [[D3:d[0-9]+]], #0x1f
|
||||
; CHECK: vclz.i32 [[D1]], [[D1]]
|
||||
; CHECK: vsub.i32 [[D1]], [[D3]], [[D1]]
|
||||
; CHECK: vstr [[D1]], [r0]
|
||||
%a = load <2 x i32>, <2 x i32>* %p
|
||||
%tmp = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %a, i1 true)
|
||||
store <2 x i32> %tmp, <2 x i32>* %p
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_v4i32_zero_undef(<4 x i32>* %p) {
|
||||
; CHECK-LABEL: test_v4i32_zero_undef:
|
||||
; CHECK: vld1.64 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [r0]
|
||||
; CHECK: vneg.s32 [[Q2:q[0-9]+]], [[Q1:q[0-9]+]]
|
||||
; CHECK: vand [[Q1]], [[Q1]], [[Q2]]
|
||||
; CHECK: vmov.i32 [[Q3:q[0-9]+]], #0x1f
|
||||
; CHECK: vclz.i32 [[Q1]], [[Q1]]
|
||||
; CHECK: vsub.i32 [[Q1]], [[Q3]], [[Q1]]
|
||||
; CHECK: vst1.64 {[[D1]], [[D2]]}, [r0]
|
||||
%a = load <4 x i32>, <4 x i32>* %p
|
||||
%tmp = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %a, i1 true)
|
||||
store <4 x i32> %tmp, <4 x i32>* %p
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_v1i64_zero_undef(<1 x i64>* %p) {
|
||||
; CHECK-LABEL: test_v1i64_zero_undef:
|
||||
; CHECK: vldr [[D1:d[0-9]+]], [r0]
|
||||
; CHECK: vmov.i32 [[D2:d[0-9]+]], #0x0
|
||||
; CHECK: vmov.i64 [[D3:d[0-9]+]], #0xffffffffffffffff
|
||||
; CHECK: vsub.i64 [[D2]], [[D2]], [[D1]]
|
||||
; CHECK: vand [[D1]], [[D1]], [[D2]]
|
||||
; CHECK: vadd.i64 [[D1]], [[D1]], [[D3]]
|
||||
; CHECK: vcnt.8 [[D1]], [[D1]]
|
||||
; CHECK: vpaddl.u8 [[D1]], [[D1]]
|
||||
; CHECK: vpaddl.u16 [[D1]], [[D1]]
|
||||
; CHECK: vpaddl.u32 [[D1]], [[D1]]
|
||||
; CHECK: vstr [[D1]], [r0]
|
||||
%a = load <1 x i64>, <1 x i64>* %p
|
||||
%tmp = call <1 x i64> @llvm.cttz.v1i64(<1 x i64> %a, i1 true)
|
||||
store <1 x i64> %tmp, <1 x i64>* %p
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_v2i64_zero_undef(<2 x i64>* %p) {
|
||||
; CHECK-LABEL: test_v2i64_zero_undef:
|
||||
; CHECK: vld1.64 {[[D1:d[0-9]+]], [[D2:d[0-9]+]]}, [r0]
|
||||
; CHECK: vmov.i32 [[Q2:q[0-9]+]], #0x0
|
||||
; CHECK: vmov.i64 [[Q3:q[0-9]+]], #0xffffffffffffffff
|
||||
; CHECK: vsub.i64 [[Q2]], [[Q2]], [[Q1:q[0-9]+]]
|
||||
; CHECK: vand [[Q1]], [[Q1]], [[Q2]]
|
||||
; CHECK: vadd.i64 [[Q1]], [[Q1]], [[Q3]]
|
||||
; CHECK: vcnt.8 [[Q1]], [[Q1]]
|
||||
; CHECK: vpaddl.u8 [[Q1]], [[Q1]]
|
||||
; CHECK: vpaddl.u16 [[Q1]], [[Q1]]
|
||||
; CHECK: vpaddl.u32 [[Q1]], [[Q1]]
|
||||
; CHECK: vst1.64 {[[D1]], [[D2]]}, [r0]
|
||||
%a = load <2 x i64>, <2 x i64>* %p
|
||||
%tmp = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 true)
|
||||
store <2 x i64> %tmp, <2 x i64>* %p
|
||||
ret void
|
||||
}
|
||||
@ -1,11 +0,0 @@
|
||||
; RUN: llc -mtriple=arm-eabi -mattr=+v6t2 %s -o - | FileCheck %s
|
||||
|
||||
declare i32 @llvm.cttz.i32(i32, i1)
|
||||
|
||||
define i32 @f1(i32 %a) {
|
||||
; CHECK-LABEL: f1:
|
||||
; CHECK: rbit
|
||||
; CHECK: clz
|
||||
%tmp = call i32 @llvm.cttz.i32( i32 %a, i1 true )
|
||||
ret i32 %tmp
|
||||
}
|
||||
Loading…
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Reference in New Issue
Block a user