mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
Optimize FSEL a bit for fneg arguments. This fixes the recently added test
case so that we emit _test_fneg_sel: .LBB_test_fneg_sel_0: ; fsel f1, f1, f3, f2 blr instead of: _test_fneg_sel: .LBB_test_fneg_sel_0: ; fneg f0, f1 fneg f0, f0 fsel f1, f0, f3, f2 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21177 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
9a98a77446
commit
af4ab1b103
@ -999,7 +999,6 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
|
||||
SetCC->getCondition() != ISD::SETEQ &&
|
||||
SetCC->getCondition() != ISD::SETNE) {
|
||||
MVT::ValueType VT = SetCC->getOperand(0).getValueType();
|
||||
Tmp1 = SelectExpr(SetCC->getOperand(0)); // Val to compare against
|
||||
unsigned TV = SelectExpr(N.getOperand(1)); // Use if TRUE
|
||||
unsigned FV = SelectExpr(N.getOperand(2)); // Use if FALSE
|
||||
|
||||
@ -1009,29 +1008,31 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
|
||||
default: assert(0 && "Invalid FSEL condition"); abort();
|
||||
case ISD::SETULT:
|
||||
case ISD::SETLT:
|
||||
BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp1).addReg(FV).addReg(TV);
|
||||
return Result;
|
||||
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
|
||||
case ISD::SETUGE:
|
||||
case ISD::SETGE:
|
||||
Tmp1 = SelectExpr(SetCC->getOperand(0)); // Val to compare against
|
||||
BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp1).addReg(TV).addReg(FV);
|
||||
return Result;
|
||||
case ISD::SETUGT:
|
||||
case ISD::SETGT: {
|
||||
Tmp2 = MakeReg(VT);
|
||||
BuildMI(BB, PPC::FNEG, 1, Tmp2).addReg(Tmp1);
|
||||
BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp2).addReg(FV).addReg(TV);
|
||||
return Result;
|
||||
}
|
||||
case ISD::SETGT:
|
||||
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
|
||||
case ISD::SETULE:
|
||||
case ISD::SETLE: {
|
||||
if (SetCC->getOperand(0).getOpcode() == ISD::FNEG) {
|
||||
Tmp2 = SelectExpr(SetCC->getOperand(0).getOperand(0));
|
||||
} else {
|
||||
Tmp2 = MakeReg(VT);
|
||||
Tmp1 = SelectExpr(SetCC->getOperand(0)); // Val to compare against
|
||||
BuildMI(BB, PPC::FNEG, 1, Tmp2).addReg(Tmp1);
|
||||
}
|
||||
BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp2).addReg(TV).addReg(FV);
|
||||
return Result;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
Opc = (MVT::f64 == VT) ? PPC::FSUB : PPC::FSUBS;
|
||||
Tmp1 = SelectExpr(SetCC->getOperand(0)); // Val to compare against
|
||||
Tmp2 = SelectExpr(SetCC->getOperand(1));
|
||||
Tmp3 = MakeReg(VT);
|
||||
switch(SetCC->getCondition()) {
|
||||
|
Loading…
Reference in New Issue
Block a user