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Go through all kinds of trouble to mark 'blr' as having a predicate operand

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that takes a register and condition code.  Print these pieces of BLR the
right way, even though it is currently set to 'always'.

Next up: get the JIT encoding right, then enhance branch folding to produce
predicated blr for simple examples.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31449 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2006-11-04 05:27:39 +00:00
parent efe9f4a3b6
commit af53a87052
3 changed files with 63 additions and 13 deletions
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30
lib/Target/PowerPC/PPCAsmPrinter.cpp
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@ -236,6 +236,9 @@ namespace {
printOperand(MI, OpNo+1);
}
void printPredicateOperand(const MachineInstr *MI, unsigned OpNo,
const char *Modifier);
virtual bool runOnMachineFunction(MachineFunction &F) = 0;
virtual bool doFinalization(Module &M) = 0;
};
@ -363,6 +366,33 @@ bool PPCAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
return false;
}
void PPCAsmPrinter::printPredicateOperand(const MachineInstr *MI, unsigned OpNo,
const char *Modifier) {
assert(Modifier && "Must specify 'cc' or 'reg' as predicate op modifier!");
unsigned Code = MI->getOperand(OpNo).getImm();
if (!strcmp(Modifier, "cc")) {
switch ((PPC::Predicate)Code) {
case PPC::PRED_ALWAYS: return; // Don't print anything for always.
case PPC::PRED_LT: O << "lt"; return;
case PPC::PRED_LE: O << "le"; return;
case PPC::PRED_EQ: O << "eq"; return;
case PPC::PRED_GE: O << "ge"; return;
case PPC::PRED_GT: O << "gt"; return;
case PPC::PRED_NE: O << "ne"; return;
case PPC::PRED_UN: O << "un"; return;
case PPC::PRED_NU: O << "nu"; return;
}
} else {
assert(!strcmp(Modifier, "reg") &&
"Need to specify 'cc' or 'reg' as predicate op modifier!");
// Don't print the register for 'always'.
if (Code == PPC::PRED_ALWAYS) return;
printOperand(MI, OpNo+1);
}
}
/// printMachineInstruction -- Print out a single PowerPC MI in Darwin syntax to
/// the current output stream.
///