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Teach machine licm to CSE hoisted instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63854 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -28,6 +28,7 @@
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Compiler.h"
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@ -36,6 +37,7 @@
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using namespace llvm;
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STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops");
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STATISTIC(NumCSEed, "Number of hoisted machine instructions CSEed");
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namespace {
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class VISIBILITY_HIDDEN MachineLICM : public MachineFunctionPass {
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@ -51,6 +53,10 @@ namespace {
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bool Changed; // True if a loop is changed.
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MachineLoop *CurLoop; // The current loop we are working on.
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MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
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// For each BB and opcode pair, keep a list of hoisted instructions.
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DenseMap<std::pair<unsigned, unsigned>,
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std::vector<const MachineInstr*> > CSEMap;
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public:
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static char ID; // Pass identification, replacement for typeid
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MachineLICM() : MachineFunctionPass(&ID) {}
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@ -68,6 +74,11 @@ namespace {
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AU.addPreserved<MachineDominatorTree>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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virtual void releaseMemory() {
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CSEMap.clear();
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}
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private:
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/// IsLoopInvariantInst - Returns true if the instruction is loop
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/// invariant. I.e., all virtual register operands are defined outside of
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@ -163,13 +174,13 @@ void MachineLICM::HoistRegion(MachineDomTreeNode *N) {
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if (!CurLoop->contains(BB)) return;
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for (MachineBasicBlock::iterator
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I = BB->begin(), E = BB->end(); I != E; ) {
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MachineInstr &MI = *I++;
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MII = BB->begin(), E = BB->end(); MII != E; ) {
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MachineBasicBlock::iterator NextMII = MII; ++NextMII;
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MachineInstr &MI = *MII;
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// Try hoisting the instruction out of the loop. We can only do this if
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// all of the operands of the instruction are loop invariant and if it is
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// safe to hoist the instruction.
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Hoist(MI);
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MII = NextMII;
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}
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const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
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@ -258,17 +269,16 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
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return true;
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}
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/// HasOnlyPHIUses - Return true if the only uses of Reg are PHIs.
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static bool HasOnlyPHIUses(unsigned Reg, MachineRegisterInfo *RegInfo) {
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bool OnlyPHIUse = false;
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/// HasPHIUses - Return true if the specified register has any PHI use.
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static bool HasPHIUses(unsigned Reg, MachineRegisterInfo *RegInfo) {
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for (MachineRegisterInfo::use_iterator UI = RegInfo->use_begin(Reg),
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UE = RegInfo->use_end(); UI != UE; ++UI) {
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MachineInstr *UseMI = &*UI;
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if (UseMI->getOpcode() != TargetInstrInfo::PHI)
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return false;
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OnlyPHIUse = true;
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if (UseMI->getOpcode() == TargetInstrInfo::PHI)
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return true;
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}
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return OnlyPHIUse;
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return false;
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}
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/// IsProfitableToHoist - Return true if it is potentially profitable to hoist
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@ -283,21 +293,42 @@ bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
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!TII->isTriviallyReMaterializable(&MI)))
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return false;
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if (!TID.isAsCheapAsAMove())
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return true;
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// If the instruction is "cheap" and the only uses of the register(s) defined
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// by this MI are PHIs, then don't hoist it. Otherwise we just end up with a
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// cheap instruction (e.g. constant) with long live interval feeeding into
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// copies that are not always coalesced away.
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bool OnlyPHIUses = false;
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// If result(s) of this instruction is used by PHIs, then don't hoist it.
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// The presence of joins makes it difficult for current register allocator
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// implementation to perform remat.
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI.getOperand(i);
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if (!MO.isReg() || !MO.isDef())
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continue;
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OnlyPHIUses |= HasOnlyPHIUses(MO.getReg(), RegInfo);
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if (HasPHIUses(MO.getReg(), RegInfo))
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return false;
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}
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return !OnlyPHIUses;
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return true;
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}
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static const MachineInstr *LookForDuplicate(const MachineInstr *MI,
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std::vector<const MachineInstr*> &PrevMIs) {
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unsigned NumOps = MI->getNumOperands();
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for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) {
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const MachineInstr *PrevMI = PrevMIs[i];
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unsigned NumOps2 = PrevMI->getNumOperands();
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if (NumOps != NumOps2)
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continue;
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bool IsSame = true;
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for (unsigned j = 0; j != NumOps; ++j) {
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const MachineOperand &MO = MI->getOperand(j);
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if (MO.isReg() && MO.isDef())
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continue;
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if (!MO.isIdenticalTo(PrevMI->getOperand(j))) {
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IsSame = false;
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break;
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}
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}
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if (IsSame)
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return PrevMI;
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}
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return 0;
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}
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/// Hoist - When an instruction is found to use only loop invariant operands
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@ -320,7 +351,41 @@ void MachineLICM::Hoist(MachineInstr &MI) {
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DOUT << "\n";
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});
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CurPreheader->splice(CurPreheader->getFirstTerminator(), MI.getParent(), &MI);
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// Look for opportunity to CSE the hoisted instruction.
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std::pair<unsigned, unsigned> BBOpcPair =
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std::make_pair(CurPreheader->getNumber(), MI.getOpcode());
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DenseMap<std::pair<unsigned, unsigned>,
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std::vector<const MachineInstr*> >::iterator CI = CSEMap.find(BBOpcPair);
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bool DoneCSE = false;
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if (CI != CSEMap.end()) {
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const MachineInstr *Dup = LookForDuplicate(&MI, CI->second);
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if (Dup) {
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DOUT << "CSEing " << MI;
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DOUT << " with " << *Dup;
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI.getOperand(i);
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if (MO.isReg() && MO.isDef())
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RegInfo->replaceRegWith(MO.getReg(), Dup->getOperand(i).getReg());
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}
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MI.eraseFromParent();
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DoneCSE = true;
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++NumCSEed;
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}
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}
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// Otherwise, splice the instruction to the preheader.
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if (!DoneCSE) {
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CurPreheader->splice(CurPreheader->getFirstTerminator(),
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MI.getParent(), &MI);
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// Add to the CSE map.
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if (CI != CSEMap.end())
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CI->second.push_back(&MI);
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else {
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std::vector<const MachineInstr*> CSEMIs;
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CSEMIs.push_back(&MI);
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CSEMap.insert(std::make_pair(BBOpcPair, CSEMIs));
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}
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}
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++NumHoisted;
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Changed = true;
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