From af7da5cb993d1a2afad4816fe22c497d5adbef91 Mon Sep 17 00:00:00 2001 From: Jack Carter Date: Thu, 28 Mar 2013 23:45:13 +0000 Subject: [PATCH] [Mips Assembler] Add support for OR macro with imediate opperand Mips assembler supports macros that allows the OR instruction to have an immediate parameter. This patch adds an instruction alias that converts this macro into a Mips ORI instruction. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178316 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips64InstrInfo.td | 4 +++- lib/Target/Mips/MipsInstrInfo.td | 3 +++ test/MC/Mips/mips-alu-instructions.s | 2 ++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 1d5912a0354..dafa37558bb 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -342,7 +342,9 @@ def : InstAlias<"daddu $rs, $rt, $imm", def : InstAlias<"dadd $rs, $rt, $imm", (DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm), 1>; - +def : InstAlias<"or $rs, $rt, $imm", + (ORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm), + 1>, Requires<[HasMips64]>; /// Move between CPU and coprocessor registers let DecoderNamespace = "Mips64" in { diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 1c523d5bd83..043077fde04 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -1015,6 +1015,9 @@ def : InstAlias<"slt $rs, $rt, $imm", def : InstAlias<"xor $rs, $rt, $imm", (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>, Requires<[NotMips64]>; +def : InstAlias<"or $rs, $rt, $imm", + (ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>, + Requires<[NotMips64]>; def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; diff --git a/test/MC/Mips/mips-alu-instructions.s b/test/MC/Mips/mips-alu-instructions.s index 816138ec654..7384d19e440 100644 --- a/test/MC/Mips/mips-alu-instructions.s +++ b/test/MC/Mips/mips-alu-instructions.s @@ -13,6 +13,7 @@ # CHECK: ins $19, $9, 6, 7 # encoding: [0x84,0x61,0x33,0x7d] # CHECK: nor $9, $6, $7 # encoding: [0x27,0x48,0xc7,0x00] # CHECK: or $3, $3, $5 # encoding: [0x25,0x18,0x65,0x00] +# CHECK: ori $4, $5, 17767 # encoding: [0x67,0x45,0xa4,0x34] # CHECK: ori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x34] # CHECK: rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00] # CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00] @@ -40,6 +41,7 @@ ins $19, $9, 6,7 nor $9, $6, $7 or $3, $3, $5 + or $4, $5, 17767 ori $9, $6, 17767 rotr $9, $6, 7 rotrv $9, $6, $7