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Fix ARM isle code that optimize multiply by constants which are power-of-2 +/- 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76520 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -949,26 +949,36 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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unsigned RHSV = C->getZExtValue();
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if (!RHSV) break;
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if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
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unsigned ShImm = Log2_32(RHSV-1);
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if (ShImm >= 32)
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break;
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SDValue V = Op.getOperand(0);
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unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
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SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
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CurDAG->getTargetConstant(ShImm, MVT::i32),
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getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
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CurDAG->getRegister(0, MVT::i32) };
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return CurDAG->SelectNodeTo(N, (Subtarget->isThumb() &&
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Subtarget->hasThumb2()) ?
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ARM::t2ADDrs : ARM::ADDrs, MVT::i32, Ops, 7);
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ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
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SDValue ShImmOp = CurDAG->getConstant(ShImm, MVT::i32);
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SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
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if (Subtarget->isThumb() && Subtarget->hasThumb2()) {
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SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
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return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
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} else {
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SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
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return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
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}
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}
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if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
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unsigned ShImm = Log2_32(RHSV+1);
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if (ShImm >= 32)
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break;
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SDValue V = Op.getOperand(0);
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unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
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SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
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CurDAG->getTargetConstant(ShImm, MVT::i32),
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getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
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CurDAG->getRegister(0, MVT::i32) };
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return CurDAG->SelectNodeTo(N, (Subtarget->isThumb() &&
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Subtarget->hasThumb2()) ?
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ARM::t2RSBrs : ARM::RSBrs, MVT::i32, Ops, 7);
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ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
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SDValue ShImmOp = CurDAG->getConstant(ShImm, MVT::i32);
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SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
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if (Subtarget->isThumb() && Subtarget->hasThumb2()) {
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SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 };
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return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 5);
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} else {
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SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
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return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
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}
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}
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}
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break;
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17
test/CodeGen/ARM/mul_const.ll
Normal file
17
test/CodeGen/ARM/mul_const.ll
Normal file
@ -0,0 +1,17 @@
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; RUN: llvm-as < %s | llc -march=arm | FileCheck %s
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define i32 @t1(i32 %v) nounwind readnone {
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entry:
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; CHECK: t1:
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; CHECK: add r0, r0, r0, lsl #3
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%0 = mul i32 %v, 9
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ret i32 %0
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}
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define i32 @t2(i32 %v) nounwind readnone {
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entry:
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; CHECK: t2:
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; CHECK: rsb r0, r0, r0, lsl #3
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%0 = mul i32 %v, 7
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ret i32 %0
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}
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18
test/CodeGen/Thumb2/mul_const.ll
Normal file
18
test/CodeGen/Thumb2/mul_const.ll
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@ -0,0 +1,18 @@
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
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; rdar://7069502
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define i32 @t1(i32 %v) nounwind readnone {
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entry:
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; CHECK: t1:
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; CHECK: add r0, r0, r0, lsl #3
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%0 = mul i32 %v, 9
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ret i32 %0
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}
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define i32 @t2(i32 %v) nounwind readnone {
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entry:
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; CHECK: t2:
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; CHECK: rsb r0, r0, r0, lsl #3
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%0 = mul i32 %v, 7
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ret i32 %0
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}
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